Roger Espasa Sans

TL;DR: A vector friendly instruction format as mentioned in this paper has a plurality of fields including a base operation field, a modifier field, an augmentation operation field and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operator field, the modifier field and the alpha field.

TL;DR: In this paper, the authors describe a system, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor, where the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location.

TL;DR: In this paper, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination, where the alignment instruction is executed.

TL;DR: It is shown that sub-word SIMD architectures (like MMX) are a very costeffective solution, and that, while long vector architectures provide few improvements at a very high cost, a smart combination between vector and SIMD-like architectures is the alternative that leverages best performance at a reasonable cost.

TL;DR: In this paper, the authors describe a system, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor, where the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location.