The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

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Defect classes-an overdue paradigm for CMOS IC testing

Quiescent power supply current (I

 DDQ
 ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I

 DDQ
 testing. Next, the use of I

 DDQ
 testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

I DDQ testing: A review

Algorithms and a computer-aided design tool, called Ceres, for technology mapping of both completely specified and incompletely specified logic networks are introduced. The algorithms are based on Boolean techniques for matching, i.e., for the recognition of the equivalence between a portion of a network and library cells. A novel matching algorithm, using ordered binary decision diagrams, is described. It exploits the notion of symmetry to achieve higher computational efficiency. A matching technique that takes advantage of don't-care conditions by means of a compatibility graph is also described. A strategy for timing-driven technology mapping, based on iterative improvement, is presented. Experimental results indicate that these techniques generate good-quality solutions and require short run times and limited memory space. >

Algorithms for technology mapping based on binary decision diagrams and on Boolean operations

This article is concerned with the role of I DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with Iddq scan, timing and functional tests. To realistically fault grade I DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total Iddq failures (parts which fail Iddq regardless of whether they fail other tests as well) or unique IDdq failures (parts which fail only Iddq). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.

I DDQ testing as a component of a test suite: the need for several fault coverage metrics

This paper compares the effectiveness of Stuck Fault and Current Testing, as applied to CMOS ICs. The comparison is performed by testing sequential CMOS chips using patterns developed via both methodis, and evaluating their ability to identify faulty prciduct. The test results are then contrasted to a previous study in which a smaller, combinatorial chip was tested by the same means. The results indicate that, for the investigated set of chips, Current Testing provides a better screen of defective product for some classes of defects, while Stuck Fault Testing is more effective on others.

Stuck fault and current testing comparison using cmos chip test

Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I, testing for stuck-at faults. In addition, IDm testing will detect logically redundant and multiple stuck-at faults and improve the detection of non-stuck-at fault defects.

Ronald R. Fritzemeier

Papers

Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets.