An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.

Pipelined packet switching and queuing architecture

A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.

Logical bridging system and method

One embodiment of the present invention provides a switch. The switch includes a port that couples to a server hosting a number of virtual machines. The switch also includes a set of virtual port grouping information and a virtual port grouping mechanism. During operation, the virtual port grouping mechanism determines whether a frame is traveling from a virtual port group to the same virtual port group. If the frame is not traveling to the same virtual port group, the virtual port grouping mechanism prevents the frame from being forwarded.

Virtual port grouping for virtual cluster switching

A network device comprises a plurality of physical ports, and a packet processing pipeline coupled to the plurality of physical ports. The packet processing pipeline is configured to assign a virtual port from a plurality of virtual ports to a packet received via one of the physical ports, wherein a quantity of the plurality of virtual ports is larger than a quantity of the plurality of physical ports, and wherein, for each of at least some of the physical ports, multiple virtual ports correspond to one physical port. The packet processing pipeline is also configured to assign a virtual domain from a plurality of virtual domains to the packet based on the assigned virtual port, and process the packet based on one or more of i) the assigned virtual port, ii) the assigned virtual domain, and iii) a header field of the packet, including determining zero, one, or more physical ports to which the packet is to be forwarded.

Switching Apparatus and Method Based on Virtual Interfaces

A system and method for policing one or more flows of a data stream of packets associated with differing transmission protocols. The current capacity level for each flow is determined, as is the packet protocol associated with each packet. A packet parameter in the packet that is indicative of the bandwidth consumption of the packet is identified. The packet parameter is converted to a predetermined format if the packet is not associated with a predetermined packet protocol. A common bandwidth capacity test is performed to determine whether the packet is conforming or non-conforming, and is a function of the packet parameter and the current bandwidth capacity level.

System and method for policing multiple data flows and multi-protocol data flows

A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented. The method performed by the apparatus includes: determining a packet frame type of the packet received; selectively extracting packet header field values specific to a packet frame type, the extracted packet header field value including packet addressing information; ascribing to the packet a preliminary action to be performed in respect of the packet; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into one of a plurality of packet flows; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet in accordance with the switch response. Advantages are derived from: pipelined processing of packets which enables short-cutting the rest of the processing for improper packets; a flexible frame type determination which is fast for well know frame types yet flexible in support of new frame types delaying obsolescence of a particular implementation; an early determination of a processing action which is successively refined by subsequent stages; a combined Layer-2 and Layer-3 network addressing search engine operating on short bit length indexed Layer-2 and Layer-3 network addresses reducing network address table storage requirements, requiring a reduced data transfer bandwidth for network address table access, a large external hashed primary network address table, and a small internal secondary network address table; an early determination of a switch response; and packet-classification-based switch response and packet header modification.

Combined pipelined classification and address search method and apparatus for switching environments

A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Method and apparatus providing rapid end-to-end failover in a packet switched communications network

A method of utilizing shared memory resources in switching Protocol Data Units (PDUs) at a data switching node is presented The method includes reserving: a temporary memory storage portion for storing PDUs prior to queuing for processing thereof, a Class-of-Service memory storage portion to provide support Quality-of-Service guarantees, a shared memory-pool portion and an input port memory storage portion enabling non-blocking input port flow control Provisions are made for PDU discard decisions to be delayed until after PDU headers are inspected subsequent to the receipt of each PDU Provisions are made for well-behaved data flows conveyed via an input port to be protected against blocking from misbehaving data flows conveyed via other input ports of the data switching node The advantages are derived from a memory management scheme which can be equally applied in a PDU discard and a flow control environment to reduce PDU discard instances at a data network node implementing the memory management scheme while reducing memory storage requirements

Buffer management for support of quality-of-service guarantees and data flow control in data switching

A credit-based pacing scheme for heterogeneous speed frame forwarding. A control logic controls the transmission of data between a source device and a destination device in accordance with a handshaking protocol. Pacing logic paces the transmission of the data from the source device to the destination device to prevent congestion in the switching fabric. A credit scheme is used to arbitrate among multiple pacing modules per device, each forwarding data at a different rate.

Credit-based pacing scheme for heterogeneous speed frame forwarding

A protocol and header format of a network architecture for communication between a plurality of network devices. In particular, the data frame is resolved at the source device to ascertain the data frame type, and the data frame is forwarded with a virtual network identifier and priority information from the source device to a destination device of the network. The forwarded data frame also includes control information.

Rong-Feng Chang

Papers

Combined pipelined classification and address search method and apparatus for switching environments

Method and apparatus providing rapid end-to-end failover in a packet switched communications network

Buffer management for support of quality-of-service guarantees and data flow control in data switching

Credit-based pacing scheme for heterogeneous speed frame forwarding

Fast data path protocol for network switching