The invention can enable monitoring of the display of content by a computer system. Moreover, the invention can enable monitoring of the displayed content to produce monitoring information from which conclusions may be deduced regarding the observation of the displayed content by an observer. The invention can also enable monitoring of the display at a content display site of content that is provided by a content provider site over a network to the content display site. Additionally, the invention can enable the expeditious provision of updated and/or tailored content over a network from a content provider site to a content display site so that the content provider's current and appropriately tailored content is always displayed at the content display site. Aspects of the invention related to transfer of content over a network are generally applicable to any type of network. However, it is contemplated that the invention can be particularly useful with a computer network, including private computer networks (e.g., America Online™) and public computer networks (e.g., the Internet). In particular, the invention can be advantageously used with computer networks or portions of computer networks over which video and/or audio content are transferred from one network site to another network site for observation, such as the World Wide Web portion of the Internet.

Content display monitor

An electronic device includes multiple power sources (102, 104, 202, 206, 302, 304) that can provide power to a load (106, 208, 306) in the electronic device. A DC-DC converter (110, 204, 310) is provided between one of the multiple power sources and the load.

Supplying power to an electronic device using multiple power sources

A method and system for obtaining a network address stored in a peripheral device, and accessing a remote device at the network address to obtain information related to the peripheral device. When the peripheral device is connected to a host computer, the stored network address is read by the host computer. The network address is preferably determined by the host computer when a peripheral device, such as a USB device, is initially connected to the host device, or when the host device with a newly connected USB is energized. The network address is then used by the host device to communicate with a remote device so that information pertaining to the peripheral device, such as a device driver for the peripheral device, can be accessed by the host device at the remote device. In addition, the host device can download or automatically execute a program stored at the remote device, download and install an application program relating to use of the peripheral device, display a Web page that includes information pertinent to the peripheral device, download documentation for the peripheral device, access help information, download and install firmware into the peripheral device and/or access other material related to the peripheral device. Access of the remote device can be fully automated or can optionally be implemented only with the permission of the user.

Method and system to access software pertinent to an electronic peripheral device based on an address stored in a peripheral device

A data storage and retrieval device and method is disclosed. The device includes at least one magnetic storage medium configured to store target data and at least one re-configurable logic device comprising an FPGA coupled to the at least one magnetic storage medium and configured to read a continuous stream of target data therefrom, having been configured with a template or as otherwise desired to fit the type of search and data being searched. The re-configurable logic device is configured to receive at least one search inquiry in the form of a data key and to determine a match between the data key and the target data as it is being read from the at least one magnetic storage medium. This device and method can perform a variety of searches on the target data including without limitation exact and approximate match searches, sequence match searches, image match searches and data reduction searches. This device and method may be provided as part of a stand-alone computer system, embodied in a network attached storage device, or can otherwise be provided as part of a computer LAN or WAN. In addition to performing search and data reduction operations, this device may also be used to perform a variety of other processing operations including encryption, decryption, compression, decompression, and combinations thereof.

Intelligent data storage and processing using fpga devices

Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle.

Method and device for high performance regular expression pattern matching

The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, translates virtual addresses from the user applications program to physical addresses, and retrieves blocks of data from the main system memory at the request of the user's code, rather than at the request of the kernel code of the host system. This is accomplished by representing the data processing commands of the user and the data associated therewith as respective command/pointer packets comprised of data processing commands and virtual pointers to the associated data in virtual memory space of the user's host system. The virtual pointers of the command/pointer packets may then be translated to physical pointers for purposes of identifying physical addresses within the main memory at which the associated data is located. The associated data may then be read from the physical address in the main memory without interrupting the host processor. Techniques are also disclosed whereby the attributes of virtual memory systems such as page fault and access fault correction may be maintained in conjunction with the user scheduled DMA technique of the invention.

User scheduled direct memory access using virtual addresses

A device for distributing a serial stream of commands and associated data to a parallel array of processing units so that the data processed by the parallel processing units can be recombined in the original order in which the serial stream was received. The command distributor of the invention hands out commands to the parallel processing units using a true "first come, first serve" algorithm using fast bus arbitration hardware. Each parallel processing unit requests data to be input when all of its data has been processed, and bus arbitration is used to prevent conflict when a plurality of requests are received. The ID of the processor to which a command is assigned is used in recombining the processed data into a serial data stream having the same order as the original. Means are also provided by which single commands which require considerable processing may be executed in parallel on more than one of the processors, with each portion of the result coming from a different processor, yet maintaining the sequentiality of the output data stream. Processing speed is further enhanced by broadcasting global commands to all processors at once.

System for distributing command/data packets tagged by their unit identifier for parallel processing by a ready processing unit and recombination

Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

Trap mode register

The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process.

System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers

Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Russ W. Herrell

Papers

User scheduled direct memory access using virtual addresses

System for distributing command/data packets tagged by their unit identifier for parallel processing by a ready processing unit and recombination

Trap mode register

System and method for directly executing user DMA instruction from user controlled process by employing processor privileged work buffer pointers

Allocating resources to partitions in a partitionable computer