Ryan A. Callison

TL;DR: In this article, the authors describe a distributed RAID system comprising a set of data banks, where each data bank has a set associated storage media and executes a similar distributed RAID application.

TL;DR: In this paper, a hardware assisted XOR operation to generate parity bits for a disk array system is described, which includes a controller that acts as an interface between a PCI bus and a DRAM that includes a writeposting cache portion and an XOR buffer portion.

TL;DR: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface as mentioned in this paper, which is used to develop parity information used with the disk array.

TL;DR: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master is described in this paper.

TL;DR: In this paper, a memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests.