Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

The present invention generally provides improved adhesion and oxidation resistance of carbon-containing layers without the need for an additional deposited layer. In one aspect, the invention treats an exposed surface of carbon-containing material, such as silicon carbide, with an inert gas plasma, such as a helium (He), argon (Ar), or other inert gas plasma, or an oxygen-containing plasma such as a nitrous oxide (N 2 O) plasma. Other carbon-containing materials can include organic polymeric materials, amorphous carbon, amorphous fluorocarbon, carbon containing oxides, and other carbon-containing materials. The plasma treatment is preferably performed in situ following the deposition of the layer to be treated. Preferably, the processing chamber in which in situ deposition and plasma treatment occurs is configured to deliver the same or similar precursors for the carbon-containing layer(s). However, the layer(s) can be deposited with different precursors. The invention also provides processing regimes that generate the treatment plasma and systems which use the treatment plasma. The carbon-containing material can be used in a variety of layers, such as barrier layers, etch stops, ARCs, passivation layers, and dielectric layers.

Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives the selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Semiconductor non-volatile memory device having a NAND cell structure

A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

Single poly memory cell and array

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Semiconductor non-volatile latch device including embedded non-volatile elements

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

Semiconductor non-volatile latch device including non-volatile elements

A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.

Ryan T. Hirose

Papers

Semiconductor non-volatile memory device having a NAND cell structure

Single poly memory cell and array

Semiconductor non-volatile latch device including embedded non-volatile elements

Semiconductor non-volatile latch device including non-volatile elements

Structure and method to prevent over erasure of nonvolatile memory transistors