A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.

Reference potential generating circuit

In a GaAs integrated circuit, a voltage reference generator includes a pair of Schottky diodes and a first, current-source connected, depletion-mode MESFET coupled in series to conduct current from a ground node to a voltage supply node. The current-source connected FET causes a constant current to flow from the ground node through the diodes, producing a constant voltage drop which generates a constant reference voltage at a reference node between the diodes and FET. A second pair of Schottky diodes is connected in series between the source of the FET and the voltage supply node, in a loop coupling the source to the gate of the FET, to provide a voltage difference Vgs across the FET proportional to voltage drop across the second pair of diodes. This voltage difference varies with fabrication process and temperature variations and causes the first FET to modify the amount of current flow to compensate so as to maintain a constant voltage drop across the first pair of diodes. A second FET is connected between the reference node and the first, current-source connected FET and has its gate coupled to the source of the first FET, either directly or through one of the second pair of diodes. Any variations in supply voltage are transmitted to the drain of the first FET to maintain a constant voltage Vds and current Ids, thereby stabilizing the reference voltage against supply voltage variations and noise.

GaAs voltage reference generator

The purpose of the invention is to obtain, with a simple circuit configuration, an LED illumination device having an LED column driven by a pulsating voltage, capable of lighting with little flicker, and also having lighting control capability The LED illumination device ( 400 ) comprises: an LED column ( 210 ) including a plurality of LEDs ( 211 ) connected in series; a rectifier ( 460 ) receiving an AC power supply ( 202 ) and outputting a pulsating voltage to the LED column ( 210 ); a current limit circuit ( 420 ) connected to the LED column ( 210 ) in series and having resistor elements ( 424 to 426 ); and a control circuit ( 250 ) for controlling the current flowing through the LED column ( 210 ) by controlling the resistor elements ( 424 to 426 ) and thereby controlling the lighting of the LED column ( 210 )

Led lighting device

A voltage converting circuit has an output MIS transistor which gives a low output impedance and outputs an intermediate level of power source voltage. The output level is set with a high accuracy through a voltage dividing ratio determined by an impedance element. This impedance element is connected with a compensating MIS transistor to compensate for variations of the gate threshold voltage caused by the manufacturing process.

FET voltage reference circuit with threshold voltage compensation

Semiconductor circuit of MOS transistors for generation of the desired reference voltage over a wide range with almost no dependence on the power voltage. An enhancement type MOS transistor and 1st depression type MOS transistor are connected in series across the power voltage, and a 2nd depression type MOS transistor and resistance component connected are in series across the power voltage. The above 1st depression type MOS transistor is connected to the gate of the 2nd depression type MOS transistor, and the reference voltage is derived from the connection point of the 2nd depression type MOS transistor and the resistance component.

Ryoichi Sato

Papers

Semiconductor circuit of MOS transistors for generation of reference voltage