An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Stackable ceramic fbga for high thermal applications

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel, scanning-probe-based data-storage system, which we internally call "millipede." A very high-integration density has been achieved, even for wafer-scale transfer, thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 cantilevers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation, which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage medium). After device transfer, the system is mechanically and electrically stable up to at least 500/spl deg/C, allowing post-transfer wafer processing.

Wafer-scale microdevice transfer/interconnect: its application in an AFM-based data-storage system

Ultra-high-density interconnection technology of three-dimensional packaging

As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding using a grindstone containing diamond particles, and wafers are divided by mechanical blade dicing using a diamond blade. However, mechanical processes using diamond grits leave damage such as chipping, saw mark or residual strain on chip surfaces; thus, chip strength decreases. At chip thickness of 50 to 200 /spl mu/m, such damage has to be avoided. In this study, the relationship between chip residue damage and chip strength is examined, and novel wafer dicing and thinning technologies that realize an average chip strength have increased from 253 MPa to 1312 MPa are described.

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000001645874/c/main.pdf

Novel wafer dicing and chip thinning technologies realizing high chip strength

Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning technologies are important key technologies to achieve it. The manufacturing steps for semiconductor devices are generally classified into steps for patterning semiconductor elements in a wafer, steps for thinning a wafer, steps for dicing semiconductor elements into chips and sealing the chips in packages. Wafers are thinned by means of mechanical in-feed grinding using a grindstone containing diamond particles, resulting in spiral grinding saw marks on the backside of the wafers. Dicing wafers always causes surface chipping, dicing saw marks on the chip side and backside chipping. Such defects on chip faces become sources of cracks, decreasing chip strength. Therefore, the manufacturing process of thin chips must achieve the requirement of no damage on all chip faces. We already proposed a novel wafer thinning process namely a dicing before grinding (DBG) and DBG + mirror finish process on 56th ECTC, and also proposed a novel flip chip process for ultra thin chip on 57th ECTC. Incidentally, the thickness required for a semiconductor chip to work has not yet been determined. In this paper, the memory chip performance test results are described.

A study on chip thinning process for ultra thin memory devices

As the mobile electronics equipment moves toward higher performance and miniaturizing, each IC package is required to be stacked for saving a package mounting area on a system board. This paper describes a newly developed 3-dimensional module package using the technology of the silicon device thinning, micro flip chip bonding and two types of via connection of print circuit board for vertical wirings. These technology has realized the high density packaging of over 4 ICs stacking for practical use.

S. Akejima

Papers

Development of 3-dimensional module package, "System Block Module"