A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (Gm) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/?(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ?A switch control ramp current from a 2.5 V supply.

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

This paper describes use of a novel exponential approximation for designing dB-linear variable gain amplifiers (VGAs). The exponential function is accurately generated using a simple error-compensation technique. The dB-linear gain is controlled linearly by the gate voltage, resulting in a simple and robust VGA. The proposed dB-linear VGA fabricated in a 65-nm CMOS process achieves a total variable gain range of 76 dB and dB-linear range greater than 50 dB with ±0.5-dB gain error. Under a 1.2-V supply voltage, the current consumption of the VGA is 1.8 mA and that of the output buffer is 1.4 mA. The input-referred in-band noise density is 3.5 nV/√{Hz} and the in-band OIP3 is 11.5 dBm. Due to the very simple circuit topology, the total active area of the VGA and the output buffer is extremely small, 0.01 mm2.

Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation

A fully integrated direct-conversion tuner is implemented in 0.13 mum CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L- bands, and occupies only 7.2 mm2 die area.

https://ir.nctu.edu.tw:443/bitstream/11536/7532/1/000263918900006.pdf

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 $\mu$ m CMOS

A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.

S. Colomines

Papers

A direct-conversion receiver for DVB-H