FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

Configurable crossbars are the easiest computational structures to fabricate at the nanoscale. By creating multiple types of crossbars and assembling them into larger structures, we may implement general computation. Architectures for diode-based and transistor-based logic are presented, along with latching mechanisms. We present simulation results from defect-tolerance studies on two applications (a 3-bit adder and a 4-bit microprocessor) mapped onto defective, nanoelectronic fabrics, and outline strategies for fault tolerance.

Nanoelectronic architectures

In this paper, we first evaluate whether or not a multiple transient fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations, we show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for very deep submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

Multiple transient faults in logic: an issue for next generation ICs?

Naturally occurring and maliciously injected faults reduce the reliability of Advanced Encryption Standard (AES) and may leak confidential information We developed an invariance-based concurrent error detection (CED) scheme which is independent of the implementation of AES encryption/decryption Additionally, we improve the security of our scheme with Randomized CED Round Insertion and adaptive checking Experimental results show that the invariance-based CED scheme detects all single-bit, all single-byte fault, and 9999999997% of burst faults The area and delay overheads of this scheme are compared with those of previously reported CED schemes on two Xilinx Virtex FPGAs The hardware overhead is in the 132-273% range and the throughput is between 18-422Gbps depending on the AES architecture, FPGA family, and the detection latency One can implement our scheme in many ways; designers can trade off performance, reliability, and security according to the available resources

/pdf/invariance-based-concurrent-error-detection-for-advanced-2zvma7lsnl.pdf

Invariance-based concurrent error detection for advanced encryption standard

http://www.through-life-engineering-services.org/downloads/Khan_et_al_NFF_Part_2_RESS_2014.pdf

No Fault Found events in maintenance engineering Part 2: Root causes, technical developments and future research

Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself.

Implications of clock distribution faults and issues with screening them during manufacturing testing

In this paper we analyze the problems which may arise because of transient faults affecting the functional blocks of CMOS self-checking circuits. In particular, we consider the case of both combinational and sequential functional blocks implemented using FCMOS or domino circuits, as well as field-programmable gate-arrays (FPGAs). We will show that, in the case of FCMOS and FPGA implemented circuits, transient faults may result in output non-unidirectional errors that can not be detected by the error detecting codes that are generally used for self-checking circuits, thus requiring additional strategies to guarantee a self-checking behavior. Reversely, this is not the case for domino circuits, which can therefore be easily concurrently checked using conventional error detecting codes. Strategies possibly used for the case of FCMOS and FPGA implemented circuits are also discussed and applied to a set of benchmark circuits.

On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits

This paper proposes an on-chip detector for the on-line testing of faults affecting clock signals and making them change with incorrect duty-cycle. Our scheme is particularly suitable to be integrated within Systems-On-a-Chip (SOCs), in order to avoid their possible incorrect operation because of faults affecting clock signals, thus solving their extreme criticality in clock faults' testing. In particular, our detector is suitable to be applied to clock signals within each SOC digital core, to the clock signals at the interface between the diverse cores, as well as to those driving the DFT and BIST structures used to perform the SOC test. Our scheme features self-checking ability with respect to its possible internal faults belonging to a realistic set including stuck-ats, transistor stuck-ons, stuck-opens and resistive bridgings.

On-Chip Clock Faults' Detector

Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor we evaluate the fault models that better describe the manufacturing defects that are most likely to affect signals of the clock distribution network. The probability of these faults has been estimated by means of Inductive Fault Analysis (IFA) and has been found to be, for the majority of cases, comparable if not one order of magnitude higher than that of other most likely microprocessor faults. The effects of the most likely clock faults has then been analyzed by means of electrical level simulations. Differently from what is generally implicitly assumed, we have found that only a small percentage of these faults results in a catastrophic failure of the microprocessor, thus being possibly easily detectable during manufacturing test, while the majority results in a local failure, which cannot be detected during manufacturing test, although compromising the microprocessor correct operation and causing an unacceptable decrease in its reliability.

Evaluation of clock distribution networks' most likely faults and produced effects

This paper investigates the impact of faults affecting the clock distribution network of synchronous systems on manufacturing testing. Previous researches based on real process data and inductive fault analysis of a reference microprocessor showed that, contrary to common expectations, the majority of clock faults leads to local failures not likely to be detected by manufacturing testing, despite their ability to compromise the microprocessor operation and reliability. This paper shows that clock faults can be detected by means of conventional stuck-at, delay and transition testing in only 12% of cases and that in 10% of cases the undetected clock faults invalidate the testing procedures themselves. In addition, in the 29% of cases, clock faults are likely to cause race conditions that, although generally not considered by delay fault testing, might as well compromise system's correct operation. The possible adoption of on-line testing techniques to avoid such dangerous conditions is finally discussed.

S. Di Francescantonio

Papers

Implications of clock distribution faults and issues with screening them during manufacturing testing

On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits

On-Chip Clock Faults' Detector

Evaluation of clock distribution networks' most likely faults and produced effects

Clock faults' impact on manufacturing testing and their possible detection through on-line testing