The verification of system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, for simulation-based verification, we need a methodology that allows one to automatically generate test cases for testing concurrent and resource-competing behaviors. We introduce the use of a transfer-resource graph (TRG) as the model for test generation. From a high abstraction level, TRG is able to model the parallelism between heterogeneous interaction forms in a system. We show how TRG is used in generating test cases of resource competitions and how these test cases are structured in event-driven test programs. For coverage, TRG can be converted to a Petri net, allowing one to measure the completeness of concurrency in simulation.

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Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

System-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs. This is made possible by modelling transfers as active building blocks.

Exploiting Concurrency in System-on-Chip Verification

Nowadays functional verification of large system-on-chip has taken about 70% to 80% of the total design effort. The large amount of IP's of current SoC's makes the work of verification engineers quite hard due to the need to guarantee that the design is bug free before it is sent to tape out. In order to reduce the time spent in the functional verification and support the verification engineers, this work proposes a Hardware Abstract Layer (HAL) generator. The HAL generator is part of a methodology for SoC functional verification, which is supported by IP-XACT and aims to automate the functional verification flow. The HAL generator is able for creating C functions that allow the manipulation of registers and their fields at a very high abstraction level allowing the verification engineers to write their test cases without need to worrying about masks, macros, define and/or pointers manipulation.

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The development of a hardware abstraction layer generator for system-on-chip functional verification

This paper presents a novel modelling methodology for System-on-Chip (SoC) verification based on software techniques. This methodology facilitates the automation of test generation; it also enables the focuses being placed on system-level behaviors such as concurrency and resource-contentions. We have demonstrated the feasibility to generalize heterogeneous interactions systematically and use them as the building blocks to generate complex test-cases of real-world concurrency.

Modelling Heterogeneous Interactions in SoC Verification

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

/pdf/a-systematic-approach-to-synthesis-of-verification-test-2va2lmtgm6.pdf

A systematic approach to synthesis of verification test-suites for modular SoC designs

We present a novel approach for hardware functional verification of system on chip (SoC). Our approach is based on the use of on chip programmable processors like CPUs or DSPs to generate test programs for hardware parts of the design. Traditionally test programs are written at a low level using specific functions for hardware accesses. This method is time consuming and error prone as tests are hand written. We introduce a method allowing the use of high level software test programs. The link between hardware and software is achieved by using a custom operating system. We focus on the benefits that are obtained by handling high level test programs.

S. Francois

Papers

Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)