This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Design and optimization of a fully integrated high data rate tranceiver in 90nm CMOS technology for on-chip UWB wireless interconnect system

This paper presents a case study of LNA design at 30 GHz. Two single-stage LNA topologies are implemented, namely a magnetic feedback LNA and a cascode LNA. The simulation results reveal that a single-stage LNA can deliver adequate power gain along with low noise figure and high linearity even at mm-wave frequencies. The cascode LNA topology, using SNIM is analyzed and described in detail. The post layout simulations give a forward gain (S 21 ) of 5.9 dB, a reverse isolation (−S 12 ) of 18.1 dB, an input reflection (S 11 ) of −11.8 dB and an output reflection (S 22 ) of −11.4 dB. The NF of the circuit is 3.9 dB while the corresponding IIP3 is 4.9 dBm. The power consumption is 7.2 mW and the circuit occupies 0.37 mm2 including the pads. The design is implemented in TSMC's LP 90 nm CMOS process.

CMOS LNA design at 30 GHz — A case study

A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide 6-bit phase resolution across the entire output frequency range, and a wide-swing CMOS buffer was designed to drive the GaN power amplifier. The GaN PA features a three-stage design, featuring a differential CML buffer, push-pull inverting buffer, and a class-E switch-mode power amplifier to efficiently amplify the signal. To the authors' knowledge, this is the first fully-integrated transmitter combining CMOS and GaN technology demonstrated in literature.

A fully-integrated S/C band transmitter in 45nm CMOS/ 0.2gm GaN heterogeneous technology

A detailed explanation on the design of low-noise amplifier is given in this paper The wideband low-noise amplifiers are implemented in 018 µm CMOS technology The various designs of low-noise amplifiers, such as the LNAs which reduce power dissipation, occupy less area, and consume less power, are presented in view of this paper A low-noise amplifier design employs different methods, such as using center-tapped inductors, by interconnecting the stages, which are explained in this paper

A Clear View on Design of Low-Noise Amplifiers Using CMOS Technology

This paper presents the design of a 21 GHz UWB Differential Low Noise Amplifier The circuit is designed in IBM 13 Rashid,m CMOS Process and is simulated in Cadence Spectre The forward gain of the circuit is 972 dB at 21 GHz with a bandwidth of 4 GHz (from 19 GHz to 23 GHz) Reverse isolation is less than −264 dB and the input-output matching parameters are −26 dB and −195 dB respectively Noise Figure of the LNA is 44 dB at the center frequency The amplifier is driven by a 12 V power supply and consumes only 2076 mW power To the best of the authors' knowledge, UWB Differential Low Noise Amplifier operating above 20 GHz is rarely reported

http://ieeexplore.ieee.org/iel5/5398766/5403682/05403943.pdf

Design of a 21 GHz UWB differential low noise amplifier using .13µm CMOS process

In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectre with 0.13μm CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz Bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit achieves a NF of 2.9 dB at the center frequency and consumes only 3.38 mW of power when driven from 1.2 Vpower supply. To the best of the authors’ knowledge, a single stage LNA operating at such high frequency is yet to be reported.

A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process

The transmitted reference ultra-wideband (TR-UWB) scheme has generated considerable interest in the field of UWB radio and on-chip wireless interconnect systems This paper presents a wideband delay element (WBDE) which is a major design concern for TR-UWB transceivers and introduces a novel WBDE architecture that eliminates the need for dual bipolar power supplies A very wide range of delays of monotonic nature (100–1000ps) can be achieved by varying the dimensions of the transistors, the power supply voltage, the shunt capacitances and the number of stages in the delay chain The WBDE, designed using IBM® 90nm CMOS technology, would make the circuit implementation of TR-UWB schemes realizable

Design of a wideband delay element for transmitted reference UWB receivers

This paper demonstrates that inserting a small resistance at the drain of a cascode LNA can be the simplest way of achieving higher Bandwidth with only a slight degradation in Noise Figure. A 36.1 GHz single stage Low Noise Amplifier is designed in 0.13μm CMOS Process with a simple passive output matching circuit. The circuit is simulated using Cadence Spectre and simulation results show a forward gain (S21) of 11.4 dB at 36.1 GHz with 4.9 GHz Bandwidth. Reverse isolation is less than −24 dB, input-output matchings are −30.36 dB and −27.65 dB respectively. NF of the circuit is around 2.9 dB. Then the circuit is simulated again, this time employing a small resistance at the drain of the cscode LNA, to show that adding a small resistance at the drain of the cascode LNA is the easiest way to increase bandwidth of the circuit without significant sacrifice of noise figure. This single stage LNA consumes only 3.37 mW of power, when driven from a 1.2 V power supply. To the best of the authors knowledge Gain-Bandwidth adjusting technique of a single stage Low Noise Amplifier operating at such high frequency is yet to be reported.

https://ieeexplore.ieee.org/iel5/4801868/4809880/04809929.pdf

Gain-bandwidth adjusting technique of A 36.1 GHz single stage low noise amplifier using 0.13μm CMOS process

In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications A UWB pulse is generated using the triangular pulse generation technique The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse A maximum data rate of 25 Gb/s with transmitted reference is achieved when the pulse repetition rate of the input clock is 5 GHz The pulse width is about 60 ps and the peak-to-peak amplitude is 502 mV with −3 dB bandwidth of 20 GHz from 15 to 35 GHz The pulse generator dissipates no static current with dynamic energy consumption of only 142 pJ per pulse from 12 V supply High transmission rate and ultra low power consumption make this simple circuit attractive for on-chip wireless interconnects

S. M. Shahriar Rashid

Papers

Design of a 21 GHz UWB differential low noise amplifier using .13µm CMOS process

A 36.1 GHz Single Stage Low Noise Amplifier Using 0.13 µm CMOS Process

Design of a wideband delay element for transmitted reference UWB receivers

Gain-bandwidth adjusting technique of A 36.1 GHz single stage low noise amplifier using 0.13μm CMOS process

A simple high data rate UWB OOK pulse generator with transmitted reference for on-chip wireless interconnects