This paper presents a framework for Fiding efficient multiprocessor realizations of digital filters. Based on simple graph-theoretic concepts, a method is derived for determining the minimal sampling period of a given digital filter structure when the speed of arithmetic operations is given but the number of processing units Is unlimited. It Is shown how realistic hardware implementations can be found and evaluated by using the timing diagram of this maximal rate realization as a starting point. The minimal sampling periods of several common digital filter structures are given in terms of addition and multiplication times.

The maximum sampling rate of digital filters under hardware speed constraints

Differential pulse-code modulation (DPCM) has found many applications in both intraframe and interframe coding of images. To improve its performance, several adaptive techniques have been introduced, but they make the resulting DPCM systems very complicated. In this work, we introduce a nonlinear scheme of predictive coding to exploiting spatial redundancy and amplitude redundancy of images based on the characteristics of the human visual system. The proposed scheme consists of a novel nonlinear algorithm to generate new information and a new compandor model of uniform quantization. >

A novel DPCM algorithm using a nonlinear operator

This communication deals with the derivation of a block implementation equation for asymmetric half-plane digital filters. First, a half-plane block transformation concept is developed which is essentially a matrix formulation for the computation of the products of two-sided polynomials and one-sided power series. Using this, a basic block equation is derived for the half-plane digital filters. It is also reasoned that the block computation of half-plane filters can be accomplished only in terms of blocks of samples in a row or a column, as opposed to the computation in terms of subarrays in the case of quarter-plane filters.

https://ieeexplore.ieee.org/iel5/31/23590/01086127.pdf

Block implementation of half-plane digital filters

Several techniques are available for implementing a scalar digital filter using lattice and ladder structures which are known to yield low noise realizations. Of these, the lattice and ladder structures proposed by Gray and Markel have the advantage of being internally scaled. Block implementation of a scalar digital filter offers a number of advantages. In this paper, new algorithms to realize block digital filters in the form of cascaded lattice or ladder two-pairs are proposed. Block lattice and ladder structures similar to Gray and Markel's scalar structure are obtained by using Levinson recursion. Also, normalized block lattice and ladder structures are developed.

Realization of digital transfer functions using cascaded lattice and ladder block structures

The development of a block state-structure with minimum round-off noise subject to l 2 -norm dynamic range constraint is outlined. The pertinent equations for scaling and for round-off noise analysis of block-state structures are first derived. Next, a lower bound and the global minimum of the output noise due to the round-off of the block-state variables are derived. A method of deriving the minimum round-off noise block state-structure is outlined. A numerical example is included. With regard to computational complexity and overall noise performance, the block state realization of recursive digital filters is shown to be superior.

S. Mitra

Papers

Block-state recursive digital filters with minimum round-off noise