Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC.

A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Floating-point arithmetic plays major role in computer systems. Many of the digital signal processing applications use floating-point algorithms for execution of the floating-point computations and every operating system is answerable practically for floating-point special cases like underflow and overflow. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts, Sign part, and Exponent part and Mantissa part. The most significant bit of the number is a sign bit and it is a 1-bit length. Next 8-bits represent the exponent part of the number and next 23-bits represent the mantissa part of the number. Mantissa part needs large 24-bit multiplication. The performance of the single-precision floating point number mostly based on the occupied area and delay of the multiplier. In this paper, a novel approach for single-precision floating multiplier is developed by using Urdhva Tiryagbhyam technique and different adders to decrease the complexity of mantissa multiplication. This requires less hardware for multiplication compared to that conventional multipliers and used different regular adders like carry select, carry skip adders and parallel prefix adders for exponent addition. Further, the performance parameters comparison was done in terms of area and delay. All modules are coded by using Verilog HDL and simulated with Xilinx ISE tool.

Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders

Compressor models are used to perform arithmetic operations like multiplication, addition etc. in digital signal processing applications such as Fast Fourier Transform, Convolution and Filtering. In order to achieve the high speed, the optimization takes place in all abstraction levels. In this paper, single precision floating point multiplication is developed using different compressor architectures to achieve high speed. Further, first, floating point multipliers are developed with normal 4:2 conventional compressors using XOR gates and further the same multipliers are developed using modified Compressors with XOR-XNOR gates and Multiplexers to achieve optimized delay and area. All the models are coded with Verilog HDL and implemented using Xilinx ISE.

Comparative analysis of single precision floating point multiplication using compressor techniques

FFT is one of the most widely-used algorithms in signal processing and communications applications. Although its realization in hardware-efficient FFT designs has been studied, there is still room to further reduce the complexity of FFT architectures by exploring more efficient expressions of twiddle factors in FFT. In this paper, a new 16-point FFT architecture is designed. A twiddle factor merging method is proposed to reduce the number of multiplications, additions and subtractions used in the design. To further improve the design, we apply a common subexpression sharing scheme to optimize the hardware resource sharing among the twiddle factors. Compared with previously published method, the proposed 16-point FFT architecture gains 25.4% and 14% improvement on hardware cost and delay respectively.

A New Twiddle Factor Merging Method for Low Complexity and High Speed FFT Architecture

La mise en oeuvre de l'algorithme FFT dans une cible FPGA represente un probleme non negligeable lorsqu'il s'agit de respecter les contraintes de l'application en termes de consommation d'energie, de cout de mise en place, de surface occupee, et de vitesse de calcul. Cet article etend l'utilisation de Radix-k a une structure appropriee d'un filtre base sur un vecteur principal d’un composant d’une matrice FFT 2D rearrangee a l'aide de la decomposition DIT (Decimation In Time, decimation en temps). Les resultats obtenus ont demontre que la structure proposee est plus efficace que celles basees sur la retroaction quand plusieurs sequences paralleles d'entree doivent etre traitees. Mots-cles: Transformee de Fourier rapide (FFT) , architecture processeur FFT – FPGA, OFDM, mise en oeuvre en temps reel English Title:  FFT processor implementation scheme for OFDM applications English Abstract The implementation of the FFT algorithm in an FPGA target represents a significant problem when it comes to meeting the constraints of the application in terms of energy consumption, cost of implementation, occupied area, and calculation speed. This work extends the use of Radix-k to an appropriate filter structure based on principal vector ofa component having 2D FFT matrix rearranged using DIT (time decimation) decomposition. The obtained results demonstrated that the proposed structure is more efficient than those based on feedback when multiple parallel input sequences are to be processed. Keywords: Fast Fourier Transform (FFT) - FFT processor architecture - FPGA - OFDM, real time implementation

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Mise en oeuvre d’un processeur FFT pour des applications OFDM

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) act as primary blocks in most of the digital signal processing applications. These two operations have undergone numerous advancements in terms of software implementation. However, there is a dearth of hardware implementation of the same, due to the involvement of floating point complex numbers. Existing Fast Fourier Transform /Inverse Fast Fourier Transform implementations mostly deal with integer data only and are incompatible with floating point data. The need of the hour is a design that can operate on floating point numbers and also achieves maximum efficiency, minimum hardware utilization and high data precision. This paper proposes implementation of a novel complex floating point arithmetic operations namely addition and multiplication. The proposed floating point adders and multipliers are used in developing 16 point Fast Fourier Transform and Inverse Fast Fourier Transform blocks. The proposed design eliminates hardware redundancy by intelligently manipulating the inputs and there by reduces the area required for implementation. The existing design and proposed design of the complex floating point multiplier is compared on the Cadence platform. Analysis of the obtained results show that the proposed design of the complex floating point multiplier as compared to the existing design, is optimal in terms of number of cells, number of gates, path delay, cell area and produces highly precise results.

S Mohith

Papers

Area and time optimized realization of 16 point FFT and IFFT blocks by using IEEE 754 single precision complex floating point adder and multiplier