A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8- mu m BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm*15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs. >

A 300-MOPS Video Signal Processor With A Parallel Architecture

The architecture of a single-chip video DSP capable of attaining a maximum performance of 300-MOPS (mega operations per second) using 0.8- mu m CMOS technology is described. The DSP is designed for the many applications regarding p*64 kb/s single-board video codecs based on DSPs that have roughly ten times the performance of conventional DSPs. Highly parallel architectures that allow four pipelined processing units to be integrated into one chip are studied extensively. The authors consider data path configurations, program sequencing control, and microinstructions that effectively support multiple pipeline processing. A prototype DSP is fabricated using 0.8- mu m CMOS technology, and some performance evaluations are presented. >

Architecture and implementation of a highly parallel single-chip video DSP

This chapter describes multiple digital signal processors (DSPs) to be applied for standardized p × 64 kbit/sec video codecs. First, the role of parallel processing with multiple DSPs is discussed which is required to achieve several hundred MOPS processing capability necessary for video coding in real time. Two approaches for implementing a video codec using multiple DSPs (the functional approach and the distributed approach) are then presented. The system configurations and DSP structures of these approaches are compared by examining recently announced video codecs. This is followed by an in-depth description of our single board video codec with its high performance multiple DSP system and the software to control the system. An application of the codec in the form of a visual telephone is also presented. We conclude by discussing future trends in DSP for video processing in terms of view of VLSI technology progress.

Multiprocessor DSPs for Low Bit Rate Video Codec

A video codec based on CCITT's standardized p*64 video coding algorithm and communication protocol has been developed for ISDN H0 rate transmission. The codec is fabricated on two 280-mm*280-mm boards and is composed of new DSPs, four kinds of NTSC-CIF (National Television Committee-Common Intermediate Format) mutual conversion LSIs, a transmission codec LSI, and an AD/DA (analog-to-digital/digital-to-analog) hybrid IC. The codec codes and decodes full CIF signs at a rate of 15 frames/s and communicates at an ISDN 384-kb/s rate. Application programs for the codec, such as picture reconstruction capability driven by DSPs in the coder or decoder, can be performed by using residual DSP processing power without the need for any hardware addition. >

VLSI video codec using programmable DSP

A single board video codec for ISDN B/2B channel transmission, which depends on a CCITT standardization p*64 video coding algorithm and communication protocol, has been developed. The video codec is constructed with newly designed DSPs, four kinds of NTSC-CIF (Common Intermediate Format) mutual conversion LSIs, a transmission codec LSI and an AD/DA hybrid IC. The video codec codes and decodes a full CIF signal at a frame rate of 10 frames/s and communicates over either an ISDN 64 kb/s or 2*6 64 kb/s channel. The codec is fabricated on a single small board with a size of 280 mm*280 mm. Furthermore, a desk-top prototype visual telephone terminal which uses the video codec, voice codec and NCU has been developed. >

S. Nishimura

Papers

Single board video codec for ISDN visual telephone