Fractal image compression is a novel technique for image compression with fractal geometry as its mathematical foundation.This paper presents a brief review to this compression technique.Basic fractal image compression algorithm,adaptive partitioning methods,complexity reduction methods,alternative choice of affine transformation and so on are discussed. Finally,some problems are given for further study.

Fractal Image Compression

Research in the field of fractal image processing (FIP) has increased in the current era. Edge detection of fractal images can be considered as an important domain of research in FIP. Detecting edges in different fractal images accurate manner is a challenging problem in FIP. Several methods have introduced by different researchers to detect the edges of images. However, no method works suitably under all conditions. In this chapter, an edge detection method is proposed to detect the edges of gray scale and color fractal images. This method focuses on the quantitative combination of Canny, LoG, and Sobel (CLS) edge detection operators. The output of the proposed method is produced using matrix laboratory (MATLAB) R2015b and compared with the edge detection operators such as Sobel, Prewitt, Roberts, LoG, Canny, and mathematical morphological operator. The experimental outputs show that the proposed method performs better as compared to other traditional methods. An Edge Detection Approach for Fractal Image Processing

An Edge Detection Approach for Fractal Image Processing

Real-time implementations of image processing algorithms on embedded platforms are gaining importance. In this paper, we propose an Application Specific Integrated Circuit (ASIC) architecture for the perfect reconstruction of images using wavelets with a view to extending this to denoising and feature extraction of images. An architecture that implements the Dual-Tree Wavelet Transform is presented. The architecture features a 128×128 single-port block memory and its addressing schemes, a simple upsampling/downsampling method and a folding and adding mechanism. It is implemented using 180nm technology. The results show perfect reconstruction of 128×128 grayscale images with up to 1-bit error in pixel values when compared to the corresponding input images.

Hardware Implementation of Dual-Tree Wavelet Transform Based Image Reconstruction

Medical images contain voluminous data Transmission of medical images over the Internet using low bandwidth and fast transmission is a major challenge Image compression techniques address this issue using cost-effective methods Fractal image compression is a compression technique used in digital image compression to increase the transmission rate with low bandwidth This is based on the fact that some parts of an image always resemble another part of the same image This concept is called self-similarity Fractal image compression has long encoding time of seconds and fast decoding time In this paper, we propose and implement architecture for fractal image compression This architecture has been implemented on a Xilinx Spartan-6 FPGA board and tested on medical images The proposed implementation reduces the encoding time to nanoseconds

A Hardware Implementation of Fractal Quadtree Compression for Medical Images

Digital images can be represented in different forms/representations by using Image Transforms, which are simple or complex mathematical operations on the image. These transforms finds application in compression, enhancement, pattern recognition, and feature extraction etc. Discrete Wavelet Transform (DWT) is a widely used wavelet transformation. DWT transforms image from space domain to frequency domain, where the wavelets are discretely sampled. DWT has various advantages over other image transforms such as image can be represented in multi resolution form, avoids the division of image into non-overlapping blocks, blocking artifacts are avoided to achieve a high compression ratio, better identification of data suitable for human perception, provides better localization in spatial and frequency domain. DWT implemented on software [Matlab] usually has lower throughput, which is due to high overall design cycle time. This can be improved through hardware implementation of DWT. In this paper an effective high speed DWT architecture has been designed using Distributed Arithmetic (DA) concept. The designed architecture has been simulated and synthesized by using Verilog HDL for the selected device ZYNQZC706 (7z045ffg900-2). Our implementation is validated on a natural image of dimension 512∗512. This implementation reduces the overall design cycle time to 0.670 nanoseconds.

S. Padmavati

Papers

A Hardware Implementation of Fractal Quadtree Compression for Medical Images

A hardware implementation of discrete wavelet transform for compression of a natural image