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S. Pradeep

Researcher at Malnad College of Engineering

Publications -  24
Citations -  1442

S. Pradeep is an academic researcher from Malnad College of Engineering. The author has contributed to research in topics: Microstructure & Friction stir processing. The author has an hindex of 9, co-authored 19 publications receiving 893 citations. Previous affiliations of S. Pradeep include Visvesvaraya Technological University & SRM University.

Papers
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Journal ArticleDOI

Secured information sharing in supply chain management: Modified data sanitization with optimal key generation via hybrid algorithm

TL;DR: Wu et al. as discussed by the authors improved the security and privacy of a suggested "blockchain assisted supply chain management" (SCM), in which modified data sanitization and data restoration is performed with an ideal key generation technique to retain sensitive data in each block.
Book ChapterDOI

Cutting Force Analysis on Drilling of Natural Fiber Reinforced Polymer Composites Material

TL;DR: In this paper, an investigation has been carried out on natural fibre reinforced polymer composites prepared using jute fibre and isophthalic polyester matrix along with a solid lubricant.
Journal ArticleDOI

Mechanical Properties Evaluation of Friction Stir Welded AA6061-AA7075 Alloys for Different Tool pin Geometries

TL;DR: In this article, the effect of different tool pin geometries on mechanical properties of friction stir welded AA6061 and AA7075 alloys keeping the process parameters constant was investigated.
Journal ArticleDOI

Processing and Evaluation of Mechanical Properties of Coconut Coir and Rice Husk Reinforced Natural Hybrid Composites

TL;DR: In this article, a composite composite material with Rice coir fiber and Rice husk reinforced polyester hybrid composites was fabricated with various weight percentages of natural fibers namely, coconut coir (20, 15, 10, and 5%), rice husk (15, 10%, and 5%) combined with CamElect 3321 resin using hand lay-up method.
Proceedings ArticleDOI

FPGA based area efficient implementation of DDR SDRAM memory controller using verilog HDL

TL;DR: This study suggested lowering the memory controller's area by optimizing the controller using bypass registers and optimizing the memory management unit operations.