The paper describes the comparison of the characteristics of two arbitration algorithms, namely, the maximum clock frequency and chip area. These characteristics have an impact on scalability of the device in which the arbiter is used. In this paper we considered implementation of the Crossbar Switch with digit capacity of four with Round Robin Arbitration Algorithm and implementation of the Crossbar Switch with digit capacity of four with Wrapped Wavefront Arbitration Algorithm at FPGA Xilinx Artix A7 using the description in the Hardware Description Language.

Comparison Round Robin and Wrapped Wavefront Arbitration Algorithms Characteristics on the Example of the Arbitration of the Crossbar Switch

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions.

A survey on scheduling and mapping techniques in 3D Network-on-chip

The System On-Chip (SoC) is where the most extreme innovation is packed into the least possible conceivable space on a single chip. As the systems intricacy increase and will with time as per Moore’s law, several challenges are being faced by the designers such as meeting the scalability of the systems, heterogeneousness of the whole bundle with different library files and coding dialects should be bundled together, synchronizing different clock domains across the systems as different systems use different clocks, de-skewing global and regional signals with high fanout and issues in coupling the systems. In SoC, there is a high complexity due to the inseparability of the computational processes and routing. NoC (Network On-Chip) presents a proficient instrument for routing which overcomes the shortcomings of the traditional buses and interconnects to allow efficient communication across the IP (Intellectual Property) cores in SoC devices. It separates the processing elements and routing elements and allow them to operate independently to great extents. The arbitration schemes, Topology and switching mechanism are important aspects which have direct impact on performance of NoC. In this a paper, a circuit switching based low latency 3D NoC architecture is presented. Here mesh topology is used and there exists a Virtual Connection from any input port to any output port. This architecture mainly consists of Arbiter, Network Interface Module and Crossbar switch which are designed using Verilog HDL and implemented on Microsemi FPGA with Target device MPF300TS_ES1FCG1152I. The results promise a low latency, low resource utilized and high throughput router design.

S Ravi

Papers

Design and Analysis of an efficient 3D – Network On – Chip (NoC) Router