By using Elliptic Curve Cryptography (ECC), it has been recently shown that Public-Key Cryptography (PKC) is indeed feasible on resource-constrained nodes This feasibility, however, does not necessarily mean attractiveness, as the obtained results are still not satisfactory enough In this paper, we present results on implementing ECC, as well as the related emerging field of Pairing-Based Cryptography (PBC), on two of the most popular sensor nodes By doing that, we show that PKC is not only viable, but in fact attractive for WSNs As far as we know pairing computations presented in this paper are the most efficient results on the MICA2 (8-bit/73828-MHz ATmega128L) and Tmote Sky (16-bit/8192-MHz MSP-430) nodes

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NanoECC: testing the limits of elliptic curve cryptography in sensor networks

In the past few years, two important trends have evolved that could change the shape of computing: multimedia applications and portable electronics. Together, these trends will lead to a personal mobile-computing environment, a small device carried all the time that incorporates the functions of the pager, cellular phone, laptop computer, PDA, digital camera, and video game. The microprocessor needed for these devices is actually a merged general-purpose processor and digital-signal processor, with the power budget of the latter. Yet for almost two decades, architecture research has focused on desktop or server machines. We are designing processors of the future with a heavy bias toward the past. To design successful processor architectures for the future, we first need to explore future applications and match their requirements in a scalable, cost-effective way. The authors describe Vector IRAM, an initial approach in this direction, and challenge others in the very successful computer architecture community to investigate architectures with a heavy bias for the future.

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A new direction for computer architecture research

This paper describes the design of a low-power microprocessor system that can run between 8Mhz at 1.1V and 100MHz at 3.3V. The ramifications of Dynamic Voltage Scaling, which allows the processor to dynamically alter its operating voltage at run-time, will be presented along with a description of the system design and an approach to benchmarking. In addition, a more in-depth discussion of the cache memory system will be

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Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System

Memory-processor integration offers new opportunities for reducing, the energy of a system. In the case of embedded systems, where memory access patterns can typically be profiled at design time, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. In this work, we propose an algorithm for the automatic partitioning of on-chip SRAMs into multiple banks. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm computes an optimal solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%.

Layout-driven memory synthesis for embedded systems-on-chip

The results of the implementation of elliptic curve cryptography (ECC) over the field GF(p) on an 80 MHz, 32-bit ARM microprocessor are presented. A practical software library has been produced which supports variable length implementation of the elliptic curve digital signature algorithm (ECDSA). The ECDSA and a previously proposed ECC-based wireless authentication protocol are implemented using the library. Timing results show that the 160-bit ECDSA signature generation and verification operations take around 46 ms and 94 ms, respectively. With these timings, the execution of the ECC-based wireless authentication protocol takes around 140 ms on the ARM7TDMI processor, which is a widely used, low-power core processor for wireless applications.

High-speed implementation of an ECC-based wireless authentication protocol on an ARM microprocessor

This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as cellphones, disk drives and modems are demanding more performance from their controllers while still requiring low cost. By implementing a second "compressed" instruction set, Thumb reduces RISC code size and so provides 32-bit ARM RISC performance and power consumption at 8/16-bit system cost.

Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications

Portable applications such as mobile phones, pagers, and PDAs are continually growing in sophistication. This places an increasing burden on the embedded microprocessor to provide high performance while retaining low power consumption and small die size. The ARM7TDMI microprocessor has been highly successful in these application areas. However, as products grow in complexity more processing power is required while the expectation on battery life also increases. This has lead to the introduction of the ARM9 family, a range of high performance low power embedded microprocessors targeted at next generation embedded applications. This paper focuses on the implementation of 2 members of the ARM9 family, the ARM9TDMI integer core and the ARM940T cached processor. These offer performance in excess of 150 MIPS while retaining low power consumption. The evolution from the ARM7 to the ARM9 microarchitecture is described and the tradeoffs between low power consumption and high performance discussed.

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The ARM9 family-high performance microprocessors for embedded applications

Portable and handheld products require processors that consume less power than those in desktop and other powered applications. As a result, designers must analyze power use in the early stage of design both at the circuit and system levels. RISC processors, such as our ARM7TDMI, have both strengths and weaknesses as far as power consumption is concerned. From a system perspective, RISC processors should consume more power than CISC processors since RISCs need to be fed with an instruction virtually every cycle. RISC processors usually have a fixed 32bit instruction format, which forces a 32-bit memory access every cycle. Thus, the processor consumes power both in accessing the memory and in driving 32 address and 32 data wires across a PCB.

S. Segars

Papers

Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications

The ARM9 family-high performance microprocessors for embedded applications

ARM7TDMI power consumption