A hybrid approach is proposed to enhance warpage predictability of thin advanced substrates. Experimental warpage data of the substrates is first obtained under various conditions. High sensitivity measurements (a contour interval of 6.25 microns/fringe or equivalent to shadow moire with a grating of 160 lines/mm) "without" painting the surface becomes possible through the advanced shadow moire method called Shadow Moire with Non-zero Talbot Distance (SM-NT) in conjunction with the optical/digital fringe multiplication (O/DFM) method. The measured warpage is combined with an FEA approach called trace mapping to incorporate the effect of the copper trace layouts into the analysis. A hybrid model is created through calibration of the properties most critical to warpage, and the warpage values of the substrates at reflow temperature are predicted.

Numerical/Experimental Hybrid Approach to Predict Warpage of Thin Advanced Substrates

Recently, the acoustic noise emanating from mobile devices becomes an important issue for user experience. The vibration of multilayer ceramic capacitors (MLCCs) mounted on printed circuit board (PCB) can transfer to the PCB and lead to acoustic noise. To mitigate singing cap acoustic noise, sometimes it has to trade off EMC/SI/PI performance during system design. So, simulation methodology is critical to predict critical acoustic issue and help design tradeoff. In this paper, a simulation methodology to provide design guideline for MLCC placement and PCB fixation with the aim to decrease board vibration is proposed. A finite element model of the multilayer PCB considering detailed copper/dielectric distribution of each layer is developed. Modal analysis is firstly performed to analyze the vibration characteristics of the bare PCB. Then the harmonic response of the board due to vibration excitation of MLCC is modeled. Based on the modal analysis result, the design guideline for MLCC placement and PCB fixation location can be established. The proposed guideline is validated through PCB harmonic response simulation.

Simulation Investigation on Acoustic Noise Caused by “Singing” Capacitors on Mobile Devices

The reliability of electronics products has become a serious problem due to the increasingly harsh environmental conditions when the products are in use. Due to demand on greater performance and higher integration in microelectronic devices, the electronics industry has been seeking suitable components, packaging and cooling techniques to achieve low-cost and high-reliability. This paper presents the experimental verifications to analyze the effect of temperature and humidity on the electronic circuit as well as evaluating the device reliability, using Xiaomi Band 2 as a real case. It is found that 125°C has been a critical temperature for the smart watch, above which the sealed plastic case ruptured easily. However, 150°C has been found to be the temperature to burst the battery. Cold storage test with a temperature of − 70°C shows that low-temperature will only cause the smartwatch to hibernate, even for up to 400 hours, after which the device will be restored to work under a room temperature. Humidity has been found to be a crucial factor in damaging the device, which changes the rubber ring and plastic case into brittle and corrodes the interconnects on printed circuit board. Further investigation into the microstructure evolution of interconnects has found that the highly accelerated stress test has caused serious cracks in solder joints and electronic components, such as, resistors and capacitors. In short, the smartwatch can work under harsher environment than the designated environmental conditions in the product manual.

Reliability analysis of smartwatch

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multihundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal co-design to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications.

Electrical and Thermal Co-Design for High-Power FPGA Packages

The authors provide a new modeling approach for the simulation of thermo-electro-mechanical stress effects within PCBs (printed circuit boards) and electronic packages. Difficult design challenges created by these effects occur throughout the full range of the product lifecycle, from the concept phase when determining a device's footprint to the analysis of reliability failures encountered after manufacturing. Given the ever-shrinking form factors of modern electronic devices and the ever-increasing chip power densities, determining mechanical deflection and stress states in thermo-electro-mechanical devices has never been more challenging. The implementation of new technology form factors, such as 2.5D interposers, will continue to push the thermal envelope, making the use of predictive modeling technologies even more critical when designing future electronic products. This paper explains the challenges and opportunities in preparing ECAD (electrical CAD) geometries for use with solvers traditionally associated with MCAD (mechanical CAD) geometries. The authors describe a new method of intelligently simplifying the ECAD geometry, which in turn greatly simplifies the MCAD model discretization. The result is a thermo-electro-mechanical stress model that benefits from fast modeling and significantly shorter solution times, but that is still highly accurate. The method can be used to correctly predict deflections (warpage), mean time to failure, and defects per million for boards with packages that have been surface mounted using a solder reflow process.

S. Shah

Papers

Electronic PCB and PKG Thermal Stress Analysis