The field control of multiple superconducting RF cavities with a single Klystron, such as the proposed RF scheme for the ILC, requires high density (number of RF channels) signal processing hardware so that vector control may be implemented with minimum group delay. The MFC (Multichannel Field Control) module is a 33- channel, FPGA based down-conversion and signal processing board in a single VXI slot, with 4 channels of high speed DAC outputs. A 32-bit, 400MHz floating point DSP provides additional computational and control capability for calibration and implementation of more complex control algorithms. Multiple high speed serial transceivers on the front panel and the backplane bus allow a flexible architecture for inter-module real time data exchanges. An interface CPLD supports the VXI bus protocol for communication to a SlotO CPU, with Ethernet connections for remote in system programming of the FPGA and DSP as well as data acquisition.

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Multichannel vector field control module for LLRF control of superconducting cavities

Evaluation of an ATCA-based LLRF system at FLASH

Future RF Control systems will require simultaneous data acquisition of up to 100 fast ADC channels at sampling rates of around 100 MHz and real time signal processing within a few hundred nanoseconds. At the same time the standardization of Low-Level RF systems are common objectives for all laboratories for cost reduction, performance optimization and machine reliability. Also desirable are modularity and scalability of the design as well as compatibility with accelerator instrumentation needs including the control system. All these requirements can be fulfilled with the new telecommunication standard ATCA when adopted to the domain of instrumentation. We describe the architecture and design of an ATCA based LLRF system for the European XFEL. Initial results of the demonstration of such a system at the FLASH user facility will be presented. Presented are the results of operating essential components of a prototype during the machine studies in January and March 2009.

Evaluation of an ATCA based LLRF system at FLASH

Future rf control systems will require simultaneous data acquisition of up to 100 fast ADC channels at sampling rates of around 100 MHz and real time signal processing within a few hundred nanoseconds. At the same time the standardization of Low-Level RF systems are common objectives for all laboratories for cost reduction, performance optimization and machine reliability. Also desirable are modularity and scalability of the design as well as compatibility with accelerator instrumentation needs including the control system. All these requirements can be fulfilled with the new telecommunication standard ATCA when adopted to the domain of instrumentation. We describe the architecture and design of an ATCA based LLRF system for the European XFEL. The operation of a prototype capable of controlling the vectorsum of 24-cavities and providing measurements of forward and reflected power are presented. CONCEPTUAL DESIGN OF LLRF BASED ON THE ATCA STANDARD The LLRF system for each rf station at the European XFEL must support acquisition of more than 100 ADC channels and data processing of all these channels on a time scale of several hundred nanoseconds to set the actuator for the klystron drive signal for cavity field control. Fast piezotuners are used to compensate the Lorentz force detuning during the pulse. The architecture of the RF system for the European XFEL is shown in Figure 1. Overall of the order of 100 applications will be implemented to ensure good field control, simple operation and high availability. The time scale for these applications range from some 100 nanoseconds over microseconds to milliseconds and seconds. The signal processing architecture with the communication links must be designed to support the required applications. The main requirements for the electronics standard are: • Modularity • Scalability • Availability of COTS components • Long term support • Low latency, high bandwidth communication links • Support signal processing in a distributed heterogeneous system of processors (FPGA, DSP, CPU) • Compatibility with accelerator control system hardware and software. The ATCA solution is composed of several ATCA carrier boards with 3 slots for AMC modules with different functionality. The carrier board includes a large FPGA (Virtex V) for low latency signal processing, and a DSP (TigerSHarc) for floating point operations. The following AMC modules types are required for rf control: • 8 channel ADC • 8 channel DAC • Vector-modulator with 2 DACs • Timing receiver with clock synthesizer • 8 channel piezo-driver • Signal processor card with FPGA and or DSP • 8 channel optical GbE The downconverters are be mounted as mezzanine cards on rear transition modules (RTM). This board is designed with only a few active components to improve the MTBF. All signals are connected from the rear of the shelf. GOALS OF THE DEMONSTRATION The various technical aspects that are verified during the demonstrations are listed in Table 1. Table 1: Aspects of Demonstration Objective Comment Analog IO Demonstrate that noise added to the signal from the input to rear transition module through Zone 3 and carrier board to the AMC module is not degraded Communication links Demonstrate that the scheme of low latency links, PCIe and GbE is functional. Operation in the accelerator environment Demonstrate that the ATCA based LLRF is functional in the noisy accelerator environment. Rear transition module Demonstrate the concept of rear transition modules with downconverters. Timing distribution Demonstrate that the timing distribution system is functional. Timing jitter Demonstrate that the measured timing jitter is adequate for LLRF control. IPMI Demonstrate the IPMI implementation. ____________________________________________ stefan.simrock@desy.de Figure 1: LLRF system architecture. WEB006 Proceedings of ICALEPCS2009, Kobe, Japan

Demonstration of an ATCA based LLRF Control System at FLASH

Middleware in accelerator and telescope control system

The key to a successful LLRF design for the International Linear Collider (ILC) relies on a combined effort from the different laboratories involved in this global project. This paper covers the ILC LLRF design progress both long term and for current test facilities around the world. The SIMCON controller board, originally developed at DESY has been successfully used at FNAL to control superconducting capture cavity I and II. LLRF team leaders from DESY, KEK and FNAL have worked together toward a common design and costing estimate for the ILC LLRF. This paper gives a general overview of the LLRF development achieved through continuous collaboration and communication between the various labs involved in the ILC LLRF design process.

Survey of LLRF development for the ILC

Since the last ICALEPCS, a small multi-region team has developed a reference design model for a control system for the International Linear Collider as part of the ILC Global Design Effort. The scale and performance parameters of the ILC accelerator require new thinking in regards to control system design. Technical challenges include the large number of accelerator systems to be controlled, the large scale of the accelerator facility, the high degree of automation needed during accelerator operations, and control system equipment requiring 'Five Nines' availability. The R&D path for high availability touches the control system hardware, software, and overall architecture, and extends beyond traditional interfaces into the technical systems. Software considerations for HA include fault detection through exhaustive out-of-band monitoring and automatic state migration to redundant systems, while the telecom industry's emerging ATCA standard - conceived, specified, and designed for High Availability - is being evaluated for suitability for ILC front-end electronics.

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S. Simrock

Papers

Survey of LLRF development for the ILC

Survey of LLRF development for the ILC

The ilc control system