A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Method for automatically generating checkers for finding functional defects in a description of a circuit

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method for automatically searching for functional defects in a description of a circuit

A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.

Selection of initial states for formal verification

An Indexed Bibliography of Genetic Algorithms in Medicine

Next Generation Test Generator (NGTG) processes require the existence of circuit models, both good and faulty, as well as the simulation of these models in order to develop tests in an effective manner. This paper addresses the issues associated with model development and simulation within an NGTG framework. The emphasis of the model development and simulation methods is on the use of commercial tools. If test automation processes are to be successfully used throughout the design and test community, the tools that designers are familiar with and use everyday must be incorporated into the NGTG processes. This paper describes the overall system briefly and the functional elements related to model development in detail. The model development portion of the system is composed of three basic functional elements: Netlist Generator (NG), Component Model Library (CML) and Automatic Model Builder (AMB). The simulation of the models is an integral part of the Automatic Test Generation (ATG) system and is presented in detail. A circuit model development process is described which allows for the creation of the good circuit model as well as the fault models necessary as part of the ATG systems. The model development and simulation approach emphasizes the use of commercial tools such as OrCAD(R)'s Capture/sup TM/, Simucad's SILOS(R) III and Intusoft/sup TM/'s ICAP/4.

Using commercial modeling and simulation tools within NGTG processes

The process outlined in this paper describes the system developed to meet the goals of the Next Generation Test Generator program, funded by the Office of Naval Research. This system takes advantage of an unsupervised pattern classification algorithm (Adaptive Resonance Theory (ART)) and a Genetic Algorithm (GA) that is combined to form an optimizing control system. The GA generates a population of test patterns (individuals). Each individual is provided as a set of timed inputs to behavior based simulations representing good and faulty systems. The response of each model (good and faulty) is recombined in the form of an image matrix with each row representing a signature of each of the different circuits. FuzzyART (Fuzzy Logic Based ART) provides a method of image recognition, extracting those images that are distinctly different from any other. Each individual generated by the GA is provided as input to the list of models, then evaluated by FuzzyART and a fitness representing the number of separate classes is formed. New test sequences evolve with increasing fault isolation and detection. The process is repeated until a maximum number of models have been identified and separated. A selective breading algorithm was included to reduce the need for large populations, thus increasing the speed to converge to the "best test". The process was demonstrated using a commercial simulator based on Verilog HDL with a simple master/slave flip-flop and a moderately complex digital circuit (real UUT).

S. Singer

Papers

Next Generation Test Generator (NGTG) for digital circuits