This paper describes the Fortran parallel task recognizer and the directed graph model upon which it is based. The recognizer is itself a Fortran program. As input the recognizer accepts source programs written in Fortran; as output the recognizer generates a set of tables which communicate to the operating system information regarding the parallel processability of source program tasks. The recognizer has been used to analyze several programs in an attempt to determine what characteristics render a program "suitable" for parallel processing. Timing studies have shown that the detailed recognizer analysis consumes a large amount of time in an attempt to answer the suitability question. For a suitable production-type program this analysis time can be distributed over the lifetime of the program. In those cases where the source program is not suitable for parallel processing, however, this analysis represents a wasted investment of valuable system resources. To circumvent this, a heuristic procedure has been developed which introduces little overhead and provides a preliminary answer to the suitability question based solely on the nature and number of source program statements. If the preliminary analysis suggests a favorable potential for the source program, then the program is subjected to the detailed analysis of the recognizer.

Program Suitability for Parallel Processing

The problem of fault detection and diagnosis of irredundant multiple-output combinational networks is discussed from a purely structural viewpoint, i.e., with the functions of the network components essentially ignored. Two structural models for a network are given in the form of labeled directed graphs. Graph theoretic concepts are introduced, and theorems are developed which give necessary conditions and sufficient conditions for the detectability of faults at particular primary outputs based solely on the structure of the network. Procedures are then presented for obtaining the structural diagnostic resolution for both line and logic module faults. Finally, an application, test point placement for increased network maintainability, is considered.

Structural Factors in the Fault Diagnosis of Combinational Networks

The structure of a circuit determines how the effects of a fault can propagate and hence affects the cost of concurrent error detection. By considering circuit structure during logic optimization, the overall cost of a concurrently checked circuit can be minimized. This report presents a new technique called structure-constrained logic optimization (SCLO) that optimizes a circuit under the constraint that faults in the resulting circuit can produce only a prescribed set of errors. Using SCLO, circuits can be optimized for various concurrent error detection schemes allowing the overall cost for each scheme to be compared. A technique for quickly estimating the size of a circuit under different structural constraints is described. This technique enables rapid exploration of the design space for concurrently checked circuits. A new method for the automated synthesis of self-checking circuit implementations for arbitrary combinational circuits is also presented. It consists of an algorithm that determines the best parity-check code for encoding the output of a given circuit, and then uses SCLO to produce the functional circuit which is augmented with a checker to form a self-checking circuit. This synthesis method provides fully automated design, explores a larger design space than other methods, and uses simple checkers. It has been implemented by making modifications to SIS (an updated version of MIS [Brayton 87a]), and results for several MCNC combinational benchmark circuits are given. In most cases, a substantial reduction in overhead compared to a duplicate-and-compare implementation is achieved.

Logic Synthesis for Concurrent Error Detection

A new algorithm is presented for finding all of the descendants of each node of an arbitrary directed linear graph. The validity of the algorithm is established and it is compared with a previously known algorithm and found to be faster for at least one class of implementations.

https://ieeexplore.ieee.org/iel5/8147/23401/01082889.pdf

S. Unger

Papers

An Algorithm for Finding the Reachability Matrix of a Directed Linear Graph