Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.

Efficient test methodologies for high-speed serial links

High Energy Physics (HEP) experiments generate high volumes of data which need to be transferred over long distance Then, for data read out, reliable and high-speed links are necessary Over the years, due to their extreme high bandwidth, serial links (especially optical) have been preferred over the parallel ones So that, now, high-speed serial links are commonly used in Trigger and Data Acquisition (TDAQ) systems of HEP experiments, not only for data transfer, but also for the distribution of trigger and control systems 
Examples of their wide use can be found at CERN, where each of the four big experiments mounted on the Large Hadron Collider (LHC) uses a huge amount of serial links in its read out system Again at LHC, the Timing, Trigger and Control system (TTC), which broadcasts the timing signals, from the LHC machine to the experiments, uses optical serial link to distribute signals over kilometers of distance (diameter of LHC is 27 Km) Also for upgrades of LHC, physical layer components and protocol chips (ASIC) have been designed and are now under development: the Versatile Link and the GBT protocol (and ASICs) whose peculiarity relies in their radiation hardness
This PhD project is intended to respond to the requests of HEP experiments, developing:
-	a high-speed self-adapting serial link, which can be easily used in different application fields;
-	the serial interface of a read out board in the end-cap region of ATLAS Experiment at LHC;
-	the interface board for the barrel read out system of the ATLAS Experiments
Both the two last projects have required the development of fixed latency, high-speed serial links
In order to take advantage of flexibility, re-programmability and system integration of SRAM-based Field Programmable Gate Array devices (FPGAs), their serializer-deserializer (SERDES) embedded modules have been chosen for the development of the links However, as a drawback, FPGA embedded SERDESes are typically designed for applications that do not require a deterministic latenc Then, an accurate study of their architecture has been necessary, in order to find a configuration and a clocking scheme to guarantee a deterministic transmission delay in data transfers

The frequency agile, auto-adaptive serial link is capable to analyze the incoming data stream, by scanning the Unit Interval, and to find the highest transmission line rate, according to a given tolerated Bit Error Ratio (BER) 
It uses a new feature (RX eye margin analysis) of the RX side of the Xilinx 7 series FPGAs high-speed transceivers (GTX/GTH), in order to measure and display the receiver eye margin after the equalizer 
When the new eye scan functionality is running, an additional sampler is activated in the GTX It acquires a new sample (Offset Sample), with programmable (horizontal and vertical) offsets from the data sample point (Data Sample) used in standard operation 
An eye scan measurement run is performed by acquiring a large number of Data Samples (which can range from tens of thousands to 1014 or more) and by counting the number of times the Offset Sample has a different value with respect to the Data Sample; the latter number is often called Error Count The BER at a specific vertical and horizontal offset is given by the ratio between the Error Count and the Sample Count By repeating the eye scan measurement for each horizontal and vertical offset in the Unit Interval (or in a part of the UI) a 2-D BER map can be produced which is usually called Statistical Eye
The auto-adaptive derail ink is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX, in order to perform a 2-D eye-scan, and takes care of the reconfiguration of the GTX parameters, in order to fully benefit from the available link bandwidth
Xilinx provides a standalone tool that allows performing the Eye Scan Analysis on the receiver side of the GTX/GTH transceiver, using the MicroBlaze Micro Controller System macro; the toolkit also includes the Eye Scan algorithm (providing the C code) Moreover, Xilinx supplies the hardware sources files for the implementation of a link based on the XAUI protocol, in which the GTXs are arranged in a loopback configuration
The original contribution of this work consists in the build-up, design and optimization of a full architecture, on top of the basic Xilinx tool, which:
 - drives the programmable ports of the GTX in order to modify the line rate of the link;
 - runs consecutive eye scans for various line rate;
 - analyses the results of the different scans, in order to find the maximum line rate sustainable by the link;
 - manages the synchronization between the transmitter and the receiver of the link, that will be needed at each line rate change
The application can be deployed as a monitoring tool in HEP experiments, in order to remotely monitor a transmission system or detect issues in the serial link physical layer An application example could be some of the many experiments at Large Hadron Collider (LHC) at CERN, which have been intensively using different serial links, both for transmission of TTC signals and for trigger and data readout 
Besides, this solution could be easily adapted in wide, different frameworks, as it can be used on top of any user’s existing link, as it has no specific requirement about link specification or protocol

The other two serial interface developed in this project are in the framework of the ATLAS experiment
ATLAS is one of the four detectors installed on the LHC proton-proton collider built at CERN It was designed to collide two opposing particle beams at an energy of 14 TeV and to reach a luminosity of 1034 cm-2/s In order to reach the design parameters, the LHC system will be upgraded in several phases In order to take advantage of the improved LHC operation, the ATLAS detector must be upgraded following the same schedule as the LHC upgrade 
The main focus of the Phase-I ATLAS upgrade (to be completed by 2018) is on the Level-1 trigger where upgrades are planned for both the muon and the calorimeter trigger systems 
In particular, for the end-cap region of the muon spectrometer, the installation of a new set of precision tracking and trigger detectors was approved, called the ‘New Small Wheels’ (NSW) It will be instrumented with micro-mesh gaseous structure detectors (MM) and small-strip Thin Gap Chambers (sTGC) These detectors will solve two points of particular importance at high luminosity: high rate of fake high-pt level-1 muon triggers, and high L1 muon rate with the current momentum threshold With the introduction of new detectors, new electronics need to be developed, in particular new trigger electronics for both the MM and sTGC I was involved in the development of serial interface of the FPGA-based sTGC trigger board that uses information from the coarse sTGC readout pads
The sTGC pad trigger board receives serial information coming from 24 front-end chips at 48 Gb/s On the board, data are deserialised, aligned and analyzed by the trigger algorithm The trigger logic processes the data and choses two candidates at each Bunch Crossing The result is then serialised and used for selective fine-grained strip readout I developed the pad trigger board interface logic The data format from the front-end chips has been agreed upon, and defines the requirements on the receiver and decoding logic The number of output lines is 24 and the data are 8B/10B formatted While the receiver uses the Xilinx Kintex-7 GTX transceivers, the output lines are driven by double data rate (DDR) shift registers at 640 Mb/s A fixed latency in the sTGC trigger chain was guaranteed through the implementation and configuration of all serialisers and deserialisers In order to test the project, I also developed a simple microprocessor-based protocol for accessing the board via terminal (rs232) A demonstrator board is now being developed
Another Phase-I Level-1 trigger upgrade consists of a new Muon to Central Trigger Processor Interface (MUCTPI) The MUCTPI receives muon candidate information from each of the muon detectors, selects muon candidates and sends them to the Central Trigger Processor (CTP) In the first runs of ATLAS, the L1 Barrel trigger candidate data were transferred to the MuCTPI via copper cables In order to cope with the trigger upgrade, serial optical links are necessary The optical links will provide a much higher bandwidth (up to 64 Gb/s) which will be used to transfer additional information from the sector logic modules, for example data for more than two muon candidates They will also provide a lower transmission latency I developed the interface board between the new MUCTPI and the Resistive Plate Chambers (RPC) muon trigger, using the Xilinx Artix-7 FPGA GTP transceivers I took care of the study of feasibility of the new serial optical transmitter and the logic for the new data format Also in this case, the fixed latency has been a requirement to be fulfilled

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Development of FPGA-based High Speed Serial Links for High Energy Physics Experiments

The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems.

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A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

In this paper, a model-based firmware generator is presented towards complex sampling schemes. The framework is capable of automatically generating a fixed-rate Shannon-compliant acquisition scheme, as well as a variable-rate compressive sensing acquisition scheme. The generation starts from a model definition, which consists of two main components, namely an acquisition sequence to implement and the platform on which the sequence should be implemented. This model is then combined with the specifications to be transformed into a functional firmware. When generating firmware for compressive sensing (CS) purposes, the defined acquisition sequence is automatically generated to implement a pseudo-random sampling scheme in agreement with the defined undersampling factor. The evaluation of the generated firmware is done by means of an example use-case, including a proposed strategy for synchronization between CS setups. This research attempts to reduce the development complexity for embedded CS to lower the threshold towards effective usage in the field.

/pdf/automated-firmware-generation-for-compressive-sensing-on-dlhyxh8w.pdf

Automated Firmware Generation for Compressive Sensing on Heterogeneous Hardware

Widely used embedded systems are applied to conquer the rapidly increasing demands of embedded systems of today, which start with a simple home device to systems with extensive architecture. They can perform a number of complex jobs in a lot of working conditions. The most common issue faced by embedded software is synchronization and it is used to maintain system integrity while conducting applications, the processing. While testing multi-PEs-based embedded systems is more complex to undertake so these issues are focused on synchronous or asynchronous real-time inter-processor communication in order to improve accuracy and timing. The research introduces a method for possible synchronization challenges across PEs.

Simulating Synchronization Issues on a Multiprocessor Embedded System for Testing

Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.

A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

Embedded systems are commonly used to meet the rapid growth in processing requirements of today's embedded system applications that range from simple home appliances to complex big architecture systems. An embedded system consisting of multiple processing elements (PEs) linked together using various types of interfaces. Many complicated tasks can be accomplished by them in different working environments. Synchronization is the typical problem with which embedded software are confronted. The processing elements require synchronization to preserve system integrity while performing the applications. Testing multi PEs-based embedded system is a challenging task; where most of the intricacies lie in testing realtime interprocessor communication i.e. synchronous or asynchronous in term of accuracy and timing. This paper is intended to provide an outline of issues affected by the need for considering synchronization on multi PEs embedded system. The paper proposes an approach that simulates possible synchronization issues across multi PEs in real-time communication. The results show that the simulation of synchronization issues on a multi PEs embedded system is a valuable approach towards creating a testing framework for embedded systems.

Sabeen Masood

Papers

A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

Simulating Synchronization Issues on a Multiprocessor Embedded System for Testing