A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

Selective operation of a multi-state non-volatile memory system in a binary mode

A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block. Wear-leveling is performed on a block being written when both total and incremental counts exceed system-wide total and incremental thresholds. The incremental-write count is cleared after a block is wear-leveled, but the total-write count is never cleared. The incremental-write count prevents moving a block again immediately after wear-leveling. The thresholds are adjusted as the system ages to provide even wear.

Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Non-volatile semiconductor memory

An RFID system and method for communicating between a host computer, one or more interrogators connected to the host computer, and a large body of transponders distributed within an area covered by the interrogators. Each transponder originally has a common identification code, and upon initialization by the host computer internally generates a unique identification code based upon an internally generated random number. The host, through the interrogators, reads each of the identification codes associated with each transponder by iteratively transmitting a read identification code command along with a controlled variable. Each transponder compares the received controlled variable to an internally generated random number, and selectively transmits its identification code based upon the outcome of this comparison. After the completion of each read identification code iteration, the host adjusts the controlled variable based upon the responses received in the previous iteration. Preferably, communications between the interrogators and the transponders are DSSS signals in TDMA format, and the transponders use the random number generator to assign a time slot for transmission of their response. Each interrogator includes an antenna system utilizing a switch matrix to connect multiple antennas having different polarizations, which ensures that all transponders within the range of the interrogator receive the signals from the interrogator. In a further aspect, the interrogators are arranged in groups, each group in nearest neighbor format, to reduce the time for reading the transponders and the emissions generated when more than one interrogator is active at the same time.

Method and system for communicating with and tracking RFID transponders

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

Arbitration of multiple transponders, such as RFID tags, occurs in an interrogation field. The arbitration process is custom-tailored for individual applications, under software control, by the transponder reader or tag reader. Different wake-up slots are calculated for each tag during successive transmission cycles based upon the tag ID and the transmission cycle number. The tag reader may also send a special command to a tag to read its data and cause the tag to become decoupled from the environment. The tags may be selectively placed in either a tag-talk-first mode or a reader-talk-first mode. Furthermore, the tag reader may send a special fast read command to the tag which includes a read request and at least one parameter of the read request.

Anticollision protocol with fast read request and additional schemes for reading multiple transponders in an rfid system

A serial EEPROM (electrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller. Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller. Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.

Serial EEPROM device and associated method for reducing data load time using a page mode write cache

Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operating a brownout detector in the device to sense EEPROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.

Power management system for serial EEPROM device

An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

Write protection security for memory device

A radio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an internal oscillator of the RFID tag device and an external PPM source such as a RFID tag reader. The PPM decoder circuit is calibrated to the difference between the external PPM frequency source (i.e., RFID tag reader) and the internal clock-oscillator of the RFID tag device, which is performed in a single measurement during one calibration symbol period.

Samuel E. Alexander

Papers

Anticollision protocol with fast read request and additional schemes for reading multiple transponders in an rfid system

Serial EEPROM device and associated method for reducing data load time using a page mode write cache

Power management system for serial EEPROM device

Write protection security for memory device

Method, system and apparatus for calibrating a pulse position modulation (ppm) decoder to a ppm signal