Increasing data rates, spectrum efficiency, and energy efficiency have been driving major advances in the design and hardware integration of RF communication networks. In order to meet the data rate and efficiency metrics, fifth-generation (5G) networks have emerged as a follow-on to 4G and projected to have $100\times $ higher wireless date rates and $100\times $ lower latency than those with current 4G networks. Major challenges arise in the packaging of radio frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs with smaller footprints and thickness. Heterogeneous integration in 3-D ultrathin packages with higher component densities and performance than with the existing 2-D packages is needed to realize such 5G systems. This article reviews the key building blocks of 5G systems and the underlying advances in packaging technologies to realize them.

A Review of 5G Front-End Systems Package Integration

The invention relates to a method and device for treating silicon wafers. In a first step, the silicon wafers (22) are conveyed flat along a continuous, horizontal conveyor belt (12, 32) and nozzles (20) or the like spray an etching solution (21) from the top onto the wafers to texture them, only little etching solution (21) being applied to the silicon wafers (22) from below. In a second step, the silicon wafers (22), which are aligned as in the first step, are wetted exclusively from below with the etching solution (35) to etch-polish them.

Method and Device for Treating Silicon Wafers

Provided is a liquid crystal display(LCD) slimming apparatus for spraying an etchant onto both sides of the LCD glass and compressing with a sponge roller, to evenly etch the LCD glass and thereby, improving flatness and preventing deterioration in optical properties of an LCD panel. The LCD glass slimming apparatus is constituted by a cassette(200) for loading plural LCD glasses, cassette conveyors(310,320), an etchant supplier, and a sponge roller(500) for compressing both sides of the LCD glass. The cassette(200) includes a cassette base(210), a pair of cassette rails, and a cassette clamp unit. The etchant supply includes an upper etchant supply tank(410), a valve(421) installed at a valve support, and a nozzle block(440). To spray the etchant supplied from the valve to both sides of the LCD glass, the nozzle block(440) is installed at a lower portion of the valve, and includes a nozzle box(441), a nozzle insertion part(442), and a nozzle(443).

Liquid crystal display glass slimming apparatus

Where a thin film formed on a glass substrate is etched with a solution containing a fluoride, insoluble residues formed by the reaction of the solution with glass substrate components adhere to the back of the substrate to cause etching non-uniformity called roller marks. So, a solution is supplied directly to supporting member for supporting the glass substrate, or concentratedly to region where the substrate and the supporting member come into contact and from a position opposite to the transporting direction of the substrate, or to both the supporting members and regions where the substrate and the supporting members come into contact. This enables the roller marks to be kept from forming, consequently making it possible to improve display quality of display devices.

Method for manufacturing display device and display device manufacturing apparatus

The state of the art high-speed digital systems for artificial intelligence, 5G mobile communication, and network servers demand enormous amount of data transmission, wider bandwidth, and faster data rate than the conventional technology. This requires packages to incorporate interconnects with very high density, but to provide cost effective manufacturing process and better performance at the same time. The new hybrid package platform based on the panel level package (PLP) interposer mounted on the high density interconnect (HDI) substrate can be a promising solution for these requirements. The PLP interposer can provide fine pitch to support considerable number of signal traces while the HDI substrate can be served as relatively inexpensive interconnects after fanning-out signals out of the interposer. Another merit of the PLP interposer is to provide lower inductance from bump to package decoupling capacitors when implementing land side capacitors underneath the PLP interposer because the PLP can have thinner substrate thickness than the Ajinomoto build-up film (ABF). The ABF interposer can be an alternative to the PLP interposer. Although the ABF interposer has thicker copper and dielectric layers than the PLP interposer, it can achieve lower resistance for the required characteristic impedance of the high-speed IO. However, the presence of joint balls between the interposer and the HDI substrate can introduce additional impedance discontinuities, which can degrade the signal integrity. Hence, optimized package design and analysis are key factors for designing such package platforms. In this paper, the PLP interposer, the ABF interposer, and the conventional package are compared for the package structure and the design optimization perspectives. Each package platform topology is illustrated, its merits and risks are discussed. For the design optimization, the traces on the interposers and the substrates are described by simple T-line models while the LC model is adopted for vertical structures including vias, pads, and balls. The benefit of using the simple model is to provide the package design guide for the performance optimization of the package and to minimize the number of package design iterations. The package design improvement will be illustrated by the insertion loss, return loss, and time domain reflectometry (TDR). Our model provides an efficient way to improve package performance, and shows good correlations with the real design.

Package Design Optimization of the Fan-out Interposer System

An apparatus and a method for etching insulating film prevents generation of spots by spraying etchant on a lower surface of the substrate as well as the upper surface.

Apparatus and method for etching insulating film

Applications including artificial intelligence, 5G mobile communication, and virtual reality require a large amount of computations, wide bandwidth, and high-speed data transmissions with very low error levels. The system-in package (SiP) becomes a promising solution to satisfy those requirements. Not only the SiP has a smaller form factor, but also it provides improved signal integrity because the shorter channel length can be achieved. The decreased distance between the logic chips and the memories lower the insertion loss, the crosstalk level, and therefore the signal degradation can be minimized. However, a high level of the system integration in the SiP and the high computing performance can result in a poor thermal management. The high computing performance requires increasing the transistor densities in various IPs, and the switching speeds of the transistors. This leads to increased power consumptions, which cause large thermal dissipations. The thermal dissipations in the package aggravate transistor performance, which yields an overall performance degradation or system malfunctions. Using heat spreader or high thermal conductive material can mitigate the thermal issues, but they are insufficient solutions. In order to improve the thermal management in the SiP, a novel SiP structure is introduced. The proposed SiP has thermal dissipation paths, which is called thermal chimney, from logic/memory dies to the heat spreader. The thermal chimney is high thermal conductive material, and it establishes a direct channel for heat flowing from the chip to the heat spreader to reduce the temperature in the package. In this study, the thermally efficient SiP geometry, how it cools down the package temperature and the manufacturing process will be described. The electrical and thermal performance will be analyzed when assuming the SiP consists of modems and DRAM memories.

Electrical and Thermal Co-Analysis of Thermally Efficient SiP for High Performance Applications

PURPOSE: A device and a method for etching an insulating film are provided to restrain spots from generating on a lower surface of a substrate by jetting an etching solution to the lower surface as well as an upper surface of the substrate, thereby improving the quality of a liquid crystal display. CONSTITUTION: A support bar(202) supports a substrate(201) on which an insulating film is formed. A plurality of rotating rollers(203A-203D) are installed at the support bar for moving the substrate in one direction. An upper surface spray nozzle(205) jets an etching solution on an upper surface of the substrate through nozzle ports(204A-204C). A lower surface spray nozzle(207) jets the etching solution on a lower surface of the substrate through another nozzle ports(206A-206C).

Sang Kyu Kim

Papers

Apparatus and method for etching insulating film

Electrical and Thermal Co-Analysis of Thermally Efficient SiP for High Performance Applications

Apparatus and method for etching isolating film

Package Design Optimization of the Fan-out Interposer System