Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics, and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT, and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting the distribution of circuit sizes. We also study canonical circuit decompositions where gates of the same kind are grouped together. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.

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Synthesis of reversible logic circuits

Multiple-valued logic, in which the number of discrete logic levels is not confined to two, has been the subject of much research over many years. The practical objective of this work has been to increase the information content of the digital signals in a system to a higher value than that provided by binary operation. In this tutorial/survey paper we will review the historical developments in this field, both in circuit realizations and in methods of handling multiple-valued design data, and consider the present state-of-the-art and future expectations.

Multiple-Valued Logic&#8212;its Status and its Future

This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm, Espresso-EXACT, for minimization of multiple-valued input, binary-valued output logic functions. Minimization of these functions is an important step in the optimization of programmable logic arrays (PLA's). In particular, the problems of two-level multiple-output minimization, minimization of PLA's with input decoders and solutions to the input encoding problem rely on efficient solutions to the multiple-valued minimization problem. Results are presented for a large class of PLA's taken from actual chip designs. These results show that the heuristic algorithm Espresso-MV comes very close to producing optimum solutions for most of the examples. Also, results from a chip design in progress at Berkeley show how important multiple-valued minimization can be for PLA optimization.

Multiple-Valued Minimization for PLA Optimization

From the Publisher:
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.
Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.
Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

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Switching Theory for Logic Synthesis

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA's and PLA's with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.

Input Variable Assignment and Output Phase Optimization of PLA's

Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA's), and the complexity of three types of PLA's is obtained by the theory of multiple- valued decomposition. A two-level PLA consists of an AND array and an OR array, and they are cascaded to perform a two-level AND-OR circuit. A PLA with decoders consists of decoders, an AND array, and an OR array. A three-level PLA consists of a D array, an AND array, and an OR array, and they are cascaded to perform a three-level OR- AND-OR circuit. It is shown that a generalized Boolean function f(X1, X2,··, Xr):X Bni → B, where B = {0,1}, is represented by a generalized Boolean expression of 2ni-valued variables X i ; and f can be directly realized by a PLA with decoders or a three-level PLA. To realize a function of n-variables (n = 2r), the following sizes are shown to be sufficient: for a two-level PLA, (n + ½) 2n; for a PLA with two-bit decoders, 4(n + 4) 2n; for a three-level PLA, 2n+ (3n + l)√2n+ 2n2Especially in the case of PLA with two-bit decoders, the following sizes are shown to be necessary and sufficient: for an arbitrary symmetric function, 3/2(n + ½) √3n; and for a parity function, (n + ½)√ 2n.

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

A conservative logic element (CLE) is a multiple-output logic element whose weight of an input vector is equal to that of the corresponding output vector, and fan-out of each output terminal is restricted to one. A CLE is a generalized model of magnetic bubble logic elements, etc. In order to realize an arbitrary function, it is necessary to use constant-supplying elements (CSE's). In this correspondence, we consider the universality of CLE's in relation to the number of CSE's.

Conservative Logic Elements and Their Universality

A recursive algorithm to obtain a complement of a sum-of-products expression for a binary function with p-valued inputs is presented. It produces at most pn/2 products for n-variable functions, whereas a conventional elementary algorithm produces O(tn·n(1-t)/2) products where t = 2P -1. It is 10-20 times faster than the elementary one when p = 2 and n = 8. For large practical-problems, it produces many fewer products than the disjoint sharp algorithm used by MINI. Appplications of the algorithm to PLA minimization are also presented.

An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs

In this correspondence, the number of functions and the number of equivalence classes of functions realized by fanout-free networks and cascades of AND'S, OR'S, and inverters are presented. For fanout-free functions, recursive formulas for T ND (n) and φ ND (n), the number of n-p-n-equivalence classes of n-variable functions and p-equivalence classes of n-variable functions, respectively, are derived. For unate cascade functions, a recursive formula for ψ ND (n), the number of n-variable functions, and formulas for U ND (n) and ψ ND (n), the number of n-p -equivalence classes and p-equivalence classes, respectively, are derived. Some asymptotic properties of ψ ND (n), U ND (n), and ψ ND (n) are also examined and it is shown that ψ ND )/ψ(n)→ 1/√2, U ND (n)/U(n)→ 1/2, and ψ ND (n)/ψ(n)→ 1/√2 as n →∞, where ψ(n) is the number of distinct unate cascade functions of up to n variables, and U(n) and ψ(n) are the number of distinct n-p-n-and p-equivalence classes of unate cascade functions of up to n variables, respectively.

Sasao

Papers

Input Variable Assignment and Output Phase Optimization of PLA's

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

Conservative Logic Elements and Their Universality

An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs

On the Number of Fanout-Free Functions and Unate Cascade Functions