An integrated circuit includes a plurality of processing stages each including processing logic 1014 , a non-delayed signal-capture element 1016 , a delayed signal-capture element 1018 and a comparator 1024 . The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014 . An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024 . The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Error recovery within processing stages of an integrated circuit

Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.

Correction of single event upset error within sequential storage circuitry of an integrated circuit

An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8 . Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

Single event upset error detection within an integrated circuit

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Error recovery within integrated circuit

Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.

Single event upset error detection within sequential storage circuitry of an integrated circuit

A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output connected to the inputs of the majority-logic circuit. The majority logic-circuit has multiple inputs connected to respective outputs of the master latches. During the period in which the master latches do not write in the corresponding input signals, an output signal of the majority-logic circuit is supplied to respective inputs of the master latches.

Flip-flop circuit having majority-logic circuit

A flip-flop circuit having a majority decision logic circuit which, even if a software error occurs, remedies the error, holds and outputs the correct content stored, has a small circuit scale, and is easily tested. The flip-flop circuit comprises multiple master latches for writing an input signal, a majority decision logic circuit having inputs connected with the outputs of the master latches, a slave latch having an input connected with the output of the majority decision logic circuit and having an output connected with the input of the majority decision logic circuit. During a period when the master latches write no input signals, the output of the majority decision logic circuit is supplied to the inputs of the master latches.

Satsukawa Yoshihiko

Papers

Flip-flop circuit having majority-logic circuit

Flip-flop circuit having majority decision logic circuit