S
Satyendra N. Biswas
Researcher at Ahsanullah University of Science and Technology
Publications - 78
Citations - 478
Satyendra N. Biswas is an academic researcher from Ahsanullah University of Science and Technology. The author has contributed to research in topics: Very-large-scale integration & System on a chip. The author has an hindex of 9, co-authored 75 publications receiving 396 citations. Previous affiliations of Satyendra N. Biswas include Kaziranga University & University of Ottawa.
Papers
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Journal ArticleDOI
An adaptive compressed MPEG-2 video watermarking scheme
TL;DR: A new compressed video watermarking procedure that embeds several binary images, decomposed from a single watermark image, into different scenes of a video sequence and incorporates a visual mask based on local image characteristics into the compressed bit streams.
Journal ArticleDOI
Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach
Sunil R. Das,J. Zakizadeh,Satyendra N. Biswas,Mansour H. Assaf,Amiya Nayak,Emil M. Petriu,Wen-Ben Jone,M. Sahinoglu +7 more
TL;DR: Oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper and is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components.
Proceedings ArticleDOI
Sensor based home automation and security system
TL;DR: The paper presents the design and implementation details of this new home control and security system based on field programmable gate array (FPGA) that works where the traditional security systems that are mainly concerned about curbing burglary and gathering evidence against trespassing fail.
Journal ArticleDOI
Space compactor design in VLSI circuits based on graph theoretic concepts
TL;DR: A new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware.
Journal ArticleDOI
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation
TL;DR: The memory cell in this paper was designed undertaking adequate measures for maintaining the stability in successive reads without any refresh operation, and the results demonstrate superb performance and sound stability of the proposedmemory cell in terms of read/write time as well as switching power consumptions.