An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Data transferred in an electronic way is vulnerable to attacks With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security features is proposed in this work Abysmal analysis of the AES algorithm implies that the security of AES lies in the S-box operations This paper presents a new approach for generating S-box values (modified S-box) and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator The AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm The traditional AES algorithm equipped with proposed novel modified S-box technique and improved key generation technique gives an avalanche effect of 60% making it invulnerable to attacks The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and compared to the existing designs resulting in significant improvement in throughput The proposed design is implemented on Spartan6 FPGA device

An efficient AES implementation using FPGA with enhanced security features

Rapid Encryption Method based on AES Algorithm for Grey Scale HD Image Encryption

This paper investigates how some of the new features of the Xilinx Virtex FPGA may be used to support efficient and optimised implementation of matrix product based on Multiply and Accumulate (MAC) such operations are frequently used in signal applications. The principle new features that have been investigated are the Block RAM and the fully digital Delay-Locked Loop (DLL) The approach used for the matrix multiplication algorithm employs the idea used in the modified Booth encoder multiplication using Wallace Trees addition. Preliminary performance results and comparisons with similar algorithms implemented on multi-FPGA platforms have shown better performance for the proposed architecture.

Accelerating matrix product on reconfigurable hardware for signal processing

Aiming at the defects of the existing analog phase-locked loop,the idea of fabricating analog phase-locked loop with imported VCXO is introduced in this article.The article also puts forward the design and selection of elements of the circuit.Test with experiment shows that feasibility of such scheme and the possibility of circuit improvement.

Phase-Locked Loop Circuit Design

Summary Matrix multiplication is the kernel operation used in many image and signal processing applications. In this paper, we present the design and Field Programmable Gate Array (FPGA) implementation of matrix multiplier architectures for use in image and signal processing applications. The designs are optimized for speed which is the main requirement in these applications. First design involves computation of dense matrixvector multiplication which is used in image processing application. The design has been implemented on Virtex-4 FPGA and the performance is evaluated by computing the execution time on FPGA. Implementation results demonstrate that it can provide a throughput of 16970 frames per second which is quite adequate for most image processing applications. The second design involves multiplication of tri-matrix (three matrices) which is used in signal processing application. The proposed design for the multiplication of three matrices has been implemented on Spartan-3 and Virtex-II Pro platform FPGAs respectively. Implementation results are presented which demonstrate the suitability of FPGAs for such applications.

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FPGA Design and Implementation of Matrix Multiplier Architectures for Image and Signal Processing Applications

Summary This paper presents an efficient hardware realization of Rijndael Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on state-of-the-art Xilinx Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a throughput of 4.34 Gbits/s using a total of 399 slices.

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Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA

Summary In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of advanced encryption standard (AES128) algorithm based on the design of high performance S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware realization of AES-128 using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of AES algorithm and makes it more complex and provides further resistance against attacks. The target hardware used in this paper is state-of-the-art Virtex-5 XC5VLX50 FPGA from Xilinx. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.

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A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

Summary A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardware description language (VHDL). The design was implemented on Xilinx Virtex-5 XC5VLX50 FPGA and the results obtained show that the proposed method provides an improved performance with 38% improvement in maximum clock frequency as well as efficient utilization of FPGA hardware resources.

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Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers

Summary Medical imaging technology requires real time efficient algorithms. The aim of this paper is to present the Field Programmable Gate Array (FPGA) based truncated multipliers delay study; implemented on Spartan-3E, Virtex-2 and Virtex-4 FPGAs using Very high speed integrated circuit Hardware Description Language (VHDL). The delay study was analyzed using analysis of variance (ANOVA) method using the software Statistical Package for Social Science (SPSS). The one way ANOVA method followed by post hoc Tukey’s test using the software SPSS with a .05 significance level was used to compare the FPGA devices. Multiple comparison tests revealed that the differences between the FPGA devices are significant with a 95% confidence level. In all three FPGA devices as the size of truncated multipliers increases their mean latency value is also increases.

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Papers

FPGA Design and Implementation of Matrix Multiplier Architectures for Image and Signal Processing Applications

Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA

A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers

Delay Study of Virtex-2, Virtex-4 and Spartan-3E Based Truncated Multipliers