It is hard to trust any data entry on online websites as some websites may be malicious, and gather data for illegal or unintended use. For example, bank login and credit card information can be misused for financial theft. To make users aware of the digital safety of websites, we have tried to identify and learn the pattern on a dataset consisting of features of malicious and benign websites. We treated the problem of differentiation between malicious and benign websites as a classification problem and applied several machine learning techniques, for example, random forest, decision tree, logistic regression, and support vector machines to this data. Several evaluation metrics such as accuracy, precision, recall, F1 score, and false positive rate, were used to evaluate the performance of each classification technique. Since the dataset was imbalanced, the machine learning models developed a bias during training toward a specific class of websites. Multiple data balancing techniques, for example, undersampling, oversampling, and SMOTE, were applied for balancing the dataset and removing the bias. Our experiments showed that after balancing the data, the random forest algorithm using the oversampling technique showed the best results in all evaluation metrics for the benign and malicious website feature dataset.

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Significance of Machine Learning for Detection of Malicious Websites on an Unbalanced Dataset

VLSI Signal Processing: a Bit-Serial Approach

The application of metabolomics toward pulmonary tuberculosis research

Weather forecasting and prediction using hybrid C5.0 machine learning algorithm

Accurate weather data are important for planning our day-to-day activities. In order to monitor and predict weather information, a two-phase weather management system is proposed, which combines information processing, bus mobility, sensors, and deep learning technologies to provide real-time weather monitoring in buses and stations and achieve weather forecasts through predictive models. Based on the sensing measurements from buses, this work incorporates the strengths of local information processing and moving buses for increasing the measurement coverage and supplying new sensing data. In Phase I, given the weather sensing data, the long short-term memory (LSTM) model and the multilayer perceptron (MLP) model are trained and verified using the data of temperature, humidity, and air pressure of the test environment. In Phase II, the trained learning model is applied to predict the time series of weather information. In order to assess the system performance, we compare the predicted weather data with the actual sensing measurements from the Environment Protection Administration (EPA) and Central Weather Bureau (CWB) of Taichung observation station to evaluate the prediction accuracy. The results show that the proposed system has reliable performance at weather monitoring and a good forecast for one-day weather prediction via the trained models.

/pdf/real-time-weather-monitoring-and-prediction-using-city-buses-2ywfm7x522.pdf

Real-Time Weather Monitoring and Prediction Using City Buses and Machine Learning.

The activities of many primary sectors depend on the weather for production, e.g. farming. The climate is changing at a drastic rate nowadays, which makes the old weather prediction methods less effective and more hectic. To overcome these difficulties, the improved and reliable weather prediction methods are required. These predictions affect a nation's economy and the lives of people. To develop a weather forecasting system that can be used in remote areas is the main motivation of this work. The data analytics and machine learning algorithms, such as random forest classification, are used to predict weather conditions. In this paper, a low-cost and portable solution for weather prediction is devised.

Weather Forecasting Using Machine Learning Algorithm

This paper presents a modified binary multiplier using Vedic mathematics. The paper proposes a modification in the previously published Vedic multiplier circuit. The suggested modified Vedic multiplication technique is more efficient in terms of delay and area. The proposed circuit is implemented in VHDL. The Mentor Graphics ModelSim tool is used for HDL simulation, and the Xilinx ISE Design Suite 14.1 is used for circuit synthesis. The simulation is done for 4-bit, 8-bit, and 16-bit multiplication operations. In this paper, the simulation waveforms are shown only for 4-bit multiplication operation based on the modified Vedic multiplication technique. The proposed method can be extended for a larger bit size. The performance evaluation in terms of speed and device utilization is compared with the previously reported Vedic multiplier architectures. The proposed design exhibits a speed improvement compared to the multiplier architectures available in literature.

Modified Binary Multiplier Circuit Based on Vedic Mathematics

A 16-bit Square Root Carry-Select Adder (SQRT CSA) is implemented and analyzed in this paper. The SQRT CSA is an architecture level modification to reduce area and power dissipation as compared to that of conventional CSA. Conventional CSA with Cin=1 block is replaced with binary-to-excess-1 converter (BEC) in the modified SQRT CSA structure. The architecture of 16-bit CSA is configured into five different stages with progressivley increasing data size. In order to realize 16-bit CSA, the basic building blocks, e.g., XOR gate, AND gate, 2:1 Mux, half adder (HA) and full adder (FA) are implemented using CMOS transmission gate (CMOS TG). The ripple carry adder (RCA) and binary-to-excess converter (BEC) of different bit sizes are also implemented. Transistor level schematics are drawn using Mentor Graphics Design Architect and simulations are carried out using Eldo with TSMC 0.35μm CMOS technology and supply voltage of 3.3 V.

CMOS implementation of efficient 16-Bit square root carry-select adder

The paper presents the HDL implementation of a novel multiplier algorithm based on the combination of Vedic mathematics and Booth-Wallace tree multiplier. An $8 \times 8$ multiplier is implemented in VHDL. The HDL code is simulated and synthesized using ModelSim and Xilinx ISE 14.1, respectively. The performance parameters of 8-bit multipliers implemented using various algorithms are compared in this paper. The comparison results exhibit that the proposed algorithm is faster than other multiplier algorithms.

Implementation of an Efficient N× N Multiplier Based on Vedic Mathematics and Booth-Wallace Tree Multiplier

Evolvable Hardware (EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. This paper presents a new approach to on-line fault tolerance via reconfiguration of the Programmable Elements (PE) mapped onto field programmable gate arrays (FPGAs). A grid of PE is programmed on the FPGA structure. A complete hardware implementation of an evolvable combinational unit for FPGAs is then performed. The proposed combinational PE grid on FPGA is used as virtual reconfigurable circuit (VRC). Cartesian Genetic Programming (CGP), genetic operators are described in Verilog - HDL and used to reprogram the VRC. In all the cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, with a maximum delay of 22.82ns (when logic level is 16) which is 40% lower than previous attempts. The design parameters of the proposed architecture are also discussed. The fault detection, based on self-checking technique can detect the faults of PEs and routing interconnections in the FPGAs concurrently with the normal system work. After locating the faulty PE, the VRC will be reconfigured using reserved PEs.

Saurabh Chaturvedi

Papers

Weather Forecasting Using Machine Learning Algorithm

Modified Binary Multiplier Circuit Based on Vedic Mathematics

CMOS implementation of efficient 16-Bit square root carry-select adder

Implementation of an Efficient N× N Multiplier Based on Vedic Mathematics and Booth-Wallace Tree Multiplier

Design and simulation of virtual reconfigurable circuit for a Fault Tolerant System