Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cds.2016.0287

Low-power and high-speed 13T SRAM cell using FinFETs

All battery-operated devices require primary memory that responds fast. By virtue of its high speed and performance, Static RAM is commonly used as cache memory and main memory in many applications. A major challenge faced in design of SRAM Cells is Read Destruction. This work introduces Transmission Gate Differential 8T (TGD8T) SRAM Cell, in which Transmission Gates are used instead of Pass Transistors in feedback path of the Existing D8T SRAM Cell in order to minimize the voltage drop across the Pass Transistors. This reduces the amount of Read Destruction and accelerates the data transmission. The transmission gates have been implemented using both High Threshold Voltage (HVT) and Low Threshold Voltage (LVT) type MOSFETS. The amount of Read Destruction in TGD8T SRAM Cell is 66.59% lesser than that of the Existing D8T SRAM Cell. Further, the transient analysis of the Read Destruction in the proposed design shows a 29.45 % reduction in the Average Transient Time. The TGD8T SRAM Cell using LVT type MOSFETs offers lesser rise time and a lower voltage drop during data transmission over the model using HVT type MOSFETs. Analysis of Static Noise Margin (SNM) of the proposed cell using N-Curve Method shows 0.13% and 5% increase in current and voltage SNMs respectively showing no compromise in noise immunity when compared to the Existing D8T SRAM Cell. The proposed TGD8T SRAM Cell is implemented in Cadence Virtuoso using gpdk 45 nm technology at a supply voltage of 0.5 V.

Speed Improvement in SRAM Cell Using Transmission Gates

The speed of the processor mainly depends upon the propagation delay caused by memory accessing operation, because of having off chip ROM memory to store the look up tables or some other frequently used data. In complex DSP processors each and every operation has to access the off chip even though it has certain amount of on chip memory for random access purpose (RAM), but in all the time RAM will not be fully utilized for random access. The usage of that memory will depends upon the operation takes place in processor. So by adding an extra word line to change the random access memory to read only memory is proposed. Here 8T transmission gate based design is used to create an array 4×4 configurable random access memory and it has an extra word line to configure the certain part of RAM to ROM to act as cache memory. By using this on chip catch memory the propagation delay occurs while accessing off chip memory will be reduced, this will reduce the bottle neck to increase the speed of the processor. Due to extra word line separate address decoder logic was designed, decoder will decide which is to be consider as RAM and which is to be consider as ROM. Transmission gate based SRAM is used to avoid the weak logic occurred while using pass transistor logic.

Design of 8T ROM embedded SRAM using double wordline for low power high speed application

Static Random Access Memories (SRAM) are designed to provide high speed access and low power consumption to the memory system. Due to aggressive scaling of devices, low power design is extremely important to meet the required constraints. MTCMOS is a technique to achieve low power consumption by employing sleep transistors to reduce the energy requirement of the cell during idle state. The conventional 12T MTCMOS based SRAM cell employs NMOS access transistors. However, this results in a delay and higher power consumption. Hence, a novel MTCMOS based 14T SRAM cell is designed to offer low power consumption with least delay. In the proposed structure, a voltage mode method and TGs are used to reduce the power dissipation. The simulations have been carried out at 45nm CMOS technology, power supply of 1v and a temperature of 25°C is taken as a reference. Results show that the power, delay, Power delay product (PDP) and Static Noise Margin (SNM) of the proposed design are improved. Tanner EDA 14.11 is used for the analysis of the circuit and Bsim4v450 model library is used as a tool for simulation. KeywordsMTCMOS, Dynamic Power, Swing Voltage, Transmission Gates.

/pdf/mtcmos-based-14t-sram-cell-optimized-for-high-performance-2cyj4nh080.pdf

MTCMOS Based 14T SRAM Cell Optimized for High Performance Applications

In this paper a 10T 1-bit static random access memory (SRAM) cell has been proposed by incorporating gated leakage transistor (GALEOR) with conventional 6T SRAM. In the proposed GALEOR technique one gated NMOS transistor is included between pull up and output and one gated PMOS transistor is added between pull down and output. Simulation of the proposed design is done in Cadence environment on 180 nm Standard CMOS process. The proposed design achieves substantial reduction in leakage power in read and write operation. Keywords—6T SRAM; static noise margin; GALEOR;leakage power

/pdf/low-power-1-bit-sram-architecture-design-using-galeor-1s344l5l71.pdf

Low Power 1 Bit SRAM Architecture Design using GALEOR Technique

Static Random Access Memory (SRAM) plays a most substantial role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay are the most common problems for SRAM cell which is basically designed for very low power application. Transmission gate is used to further reduced leakage current penetrating in the 8T SRAM cell. Comparative analysis is performed by using transmission gate. This paper represents a method for design a variability aware SRAM cell. The proposed architecture of the TG8T SRAM cell is analogous to the standard 6T SRAM cell, the only exception is that they possess full transmission gates which replace an access pass transistor. The paper studies the different parameters of TG8Twrite operation at 0.7 V like leakage current is 229.2fA, leakage power is 297.4nW, delay is 20.92ns and SNR is 4.77dB. This result performs on the cadence virtuoso tool at 45nm technology.

Saurahbh

Papers

Implementation of High Performance SRAM Cell Using Transmission Gate