Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Systems and Methods for Power Amplifiers with Voltage Boosting Multi-Primary Transformers

Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.

Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Integrated RF front end with stacked transistor switch

An impedance matching device is provided, for which the electric characteristics at an output terminal are accurately analyzed. The matching device is provided with an input detector for detecting RF voltage and current at the input terminal, and an output detector for detecting RF voltage outputted from the output terminal. The matching device also includes a controller for achieving impedance matching between a high frequency power source connected to the input terminal and a load connected to the output terminal. The impedance matching is performed by adjusting variable capacitors based on the detection data supplied from the input detector. When the impedance of the power source is matched to that of the load, the controller calculates the output impedance, RF voltage and RF current at the output terminal, based on the adjusted capacitances of the capacitors, a pre-obtained reactance-impedance data and the detection data supplied from the output detector.

Impedance matching device provided with reactance-impedance table

A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.

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Reliable normally-off III-nitride active device structures, and related methods and systems

A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Cascode circuit and integrated circuit having it

A semiconductor chip for amplification is connected between input-side and output-side matching circuits, and each of matching circuits includes balanced circuits which receive signals different in phase by 180 degrees, divided from an input signal. The balanced circuits are connected at a virtual grounding point, which is used as a grounding point sensitive to RF characteristics in an IPD. Thus, a semiconductor device can be free from influence of variations of grounding wires and can be reduced in size, weight, and cost.

Semiconductor device having balanced circuit for use in high frequency band

An internally impedance matched transistor circuit prevents low frequency oscillation during high frequency band operation. Field effect transistors and corresponding oscillation-preventing stabilization circuits are located in the same package with the stabilization circuits close to the corresponding field effect transistors. Each oscillation-preventing stabilization circuit includes a resistor and a capacitor connected in series.

Transistor with internal matching circuit

An impedance matching circuit disposed on one of input and output sides of an element to be evaluated matches I/O impedances of the element. The impedance matching circuit includes a matching substrate having a surface, a main line on the surface, passive circuits having stubs and FETs alternatingly connected in series and electrically connected to the main line to change impedance of the main line, and a plurality of switching FETs connected in series between the main line and the respective passive circuits switched on and off in accordance with characteristics of the element. The impedances of the matching substrate can be changed as required by electrically connecting the passive circuit to the main line by switching of the FETs. Even when a considerable change occurs in the I/O impedances of the element due to fabrication variations and in large signal (non-linear) operation of a power FET, I/O impedances of an evaluating object can be matched easily and promptly by appropriate switching of the FETs.

Impedance matching circuit and thin film measuring prober

We report the performance of a V-band 5-stage high power amplifier MMIC using a millimeter-wave 0.1 mum GaAs pHEMT. It has demonstrated that an output power of 28.8 dBm (759 mW) at 1 dB compression point with 17.8 dB power gain and 14.2% PAE at 59 GHz. And it delivers an output power of 28.9 dBm (776 mW) at a saturation point. These results represent, to the best of our knowledge, the highest output power and power gain for single-ended MMICs.

Seiki Goto

Papers

Cascode circuit and integrated circuit having it

Semiconductor device having balanced circuit for use in high frequency band

Transistor with internal matching circuit

Impedance matching circuit and thin film measuring prober

A V-Band High Power and High Gain Amplifier MMIC using GaAs PHEMT Technology