Seongan Lim

TL;DR: A new type of safe-error based hardware fault cryptanalysis is demonstrated which is mounted on a recently reported countermeasure against simple power analysis attack and it is emphasized that acountermeasure developed against one physical attack if not carefully examined may benefit another physical attack tremendously.

TL;DR: This article considers the problem of how to prevent RSA signature and decryption computation with a residue number system (CRT-based approach) speedup from a hardware fault cryptanalysis in a highly reliable and efficient approach and proposes two novel protocols that have comparable performance to Shamir's scheme.

TL;DR: This article considers the problem of how to prevent the fast RSA signature and decryption computation with residue number system speedup from a hardware fault cryptanalysis in a highly reliable and efficient approach and proposes a new concept of fault infective CRT computation and fault infectives CRT recombination.

TL;DR: This paper states and proves a necessary condition for the existence of a pair of desired vectors and presents an algorithm to find them and improves the efficiency of the scalar multiplication roughly about 50%.

TL;DR: It is shown that the choice of either pr qr-1, pr-1 qr+1, or pr-2qr+2 depending on the value r + s is the optimal, and comparison tables for the efficiency of RSA, the multiprime technology, Takagi's scheme, and the proposed scheme are presented.