NetFPGA SUME is the newest high performance network design platform of the NetFPGA. In this paper, the principle of implementing high speed switch on NetFPGA SUME is illustrated in detail. And an experiment to validate the speed of the NetFPGA SUME is designed utilizing the Socket transmission model. The experiment result shows that the NetFPGA SUME can realize the high speed switching and the high speed forwarding to the data.

The high-speed switching experiment based on netfpga sume

A Reconfigurable Hardware Architecture for Packet Processing

In recent times, energy consumption in communication media has been increasing drastically. In the literature, energy-saving techniques that enable network devices to enter sleep state or limit the data rate have been proposed to reduce energy costs. In our earlier work, we proposed an energy-saving technique called burst-based adaptive link rate BBALR , the simulation of which assures increased energy savings. In this paper, we have emulated the hardware implementation of BBALR and compared its performance with the outputs of other prominent energy-saving policies based on dynamic link rate adaption. The energy savings are mapped from the measured sleep time and reference power values. We have used NetFPGA as the testbed, which is a research platform for building real-time network hardware prototypes.

/pdf/emulation-of-burst-based-adaptive-link-rates-in-netfpga-4cc4e5ngf2.pdf

Shahul Hamead Haja Moinudeen

Papers

Emulation of burst-based adaptive link rates in NetFPGA towards green networking