Bifidobacteria, the initial colonisers of breastfed infant guts, are considered as the key commensals that promote a healthy gastrointestinal tract. However, little is known about the key metabolic differences between different strains of these bifidobacteria, and consequently, their suitability for their varied commercial applications. In this context, the present study applies a constraint-based modelling approach to differentiate between 36 important bifidobacterial strains, enhancing their genome-scale metabolic models obtained from the AGORA (Assembly of Gut Organisms through Reconstruction and Analysis) resource. By studying various growth and metabolic capabilities in these enhanced genome-scale models across 30 different nutrient environments, we classified the bifidobacteria into three specific groups. We also studied the ability of the different strains to produce short-chain fatty acids, finding that acetate production is niche- and strain-specific, unlike lactate. Further, we captured the role of critical enzymes from the bifid shunt pathway, which was found to be essential for a subset of bifidobacterial strains. Our findings underline the significance of analysing metabolic capabilities as a powerful approach to explore distinct properties of the gut microbiome. Overall, our study presents several insights into the nutritional lifestyles of bifidobacteria and could potentially be leveraged to design species/strain-specific probiotics or prebiotics.

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Deciphering the metabolic capabilities of Bifidobacteria using genome-scale metabolic models.

A predictive compiler uses properties of a program to decide how to optimize it. The compiler is trained on a collection of programs to derive a model which determines its actions in face of unknown codes. One of the challenges of predictive compilation is how to find good training sets. Regardless of the programming language, the availability of human-made benchmarks is limited. Moreover, current synthesizers produce code that is very different from actual programs, and mining compilable code from open repositories is difficult, due to program dependencies. In this paper, we use a combination of web crawling and type inference to overcome these problems for the C programming language. We use a type reconstructor based on Hindley-Milner's algorithm to produce ANGHABENCH, a virtually unlimited collection of real-world compilable C programs. Although ANGHABENCH programs are not executable, they can be transformed into object files by any C compliant compiler. Therefore, they can be used to train compilers for code size reduction. We have used thousands of ANGHABENCH programs to train YACOS, a predictive compiler based on LLVM. The version of YACOS autotuned with ANGHABENCH generates binaries for the LLVM test suite over 10% smaller than clang -Oz. It compresses code impervious even to the state-of-the-art Function Sequence Alignment technique published in 2019, as it does not require large binaries to work well.

AnghaBench: a suite with one million compilable C benchmarks for code-size reduction

The growing popularity of machine learning frameworks and algorithms has greatly contributed to the design and exploration of good code optimization sequences. Yet, in spite of this progress, mainstream compilers still provide users with only a handful of fixed optimization sequences. Finding optimization sequences that are good in general is challenging because the universe of possible sequences is potentially infinite. This paper describes a infrastructure that provides developers with the means to explore this space. Said infrastructure, henceforth called YaCoS, consists of benchmarks, search algorithms, metrics to estimate the distance between programs, and compilation strategies. YaCoS's features let users build learning models that predict, for unknown programs, optimization sequences that are likely to yield good results for them. In this paper, as a case study, we have used YaCoS to find good optimization sequences for LLVM, using code size as the objective function. Such study lets us evaluate three feature sets: two variations of the feature vectors proposed by Namolaru at al in 2010, plus the optimization statistics produced by LLVM. Our results show that YaCoS is able to find sequences that improve onto clang -Oz by 3.75% on average. Our experiments do not indicate a dominant feature set out of the three approaches that we have investigated---it is possible to find programs in which one of them is strictly better than the others.

YACOS: a Complete Infrastructure to the Design and Exploration of Code Optimization Sequences

Quantization is a technique to reduce the computation and memory cost of DNN models, which are getting increasingly large. Existing quantization solutions use fixed-point integer or floating-point types, which have limited benefits, as both require more bits to maintain the accuracy of original models. On the other hand, variable-length quantization uses low-bit quantization for normal values and high-precision for a fraction of outlier values. Even though this line of work brings algorithmic benefits, it also introduces significant hardware overheads due to variable-length encoding and decoding.In this work, we propose a fixed-length a daptive n umerical data t ype called ANT to achieve low-bit quantization with tiny hardware overheads. Our data type ANT leverages two key innovations to exploit the intra-tensor and inter-tensor adaptive opportunities in DNN models. First, we propose a particular data type, flint, that combines the advantages of float and int for adapting to the importance of different values within a tensor. Second, we propose an adaptive framework that selects the best type for each tensor according to its distribution characteristics. We design a unified processing element architecture for ANT and show its ease of integration with existing DNN accelerators. Our design results in $2.8\times $ speedup and $2.5\times $ energy efficiency improvement over the state-of-the-art quantization accelerators.

ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization

Asymmetric multicore processors (AMP) fall under a special subcategory of modern-day heterogeneous multicore architectures with different participating core types executing a common instruction set architecture. The innate asymmetry in the performance of different cores in AMPs poses interesting challenges. Irregular workloads, such as graph algorithms, intensify these challenges as the parallel workloads in these algorithms cannot be precisely characterized at compile time. In this paper, we propose a framework named scheduler for irregular AMPs, which optimizes the efficiency of the given AMP system for a given algorithm-graph pair by optimizing the graph representation and using a predictor to find the optimal configurations to run the algorithm-graph pair. The optimization is performed in two stages: 1) finding an optimal graph representation and 2) finding an optimal hardware configuration to run the input algorithm-graph pair. We have tested the efficiency of our system on five different graph algorithms over eight real-world and synthetic graphs. On an average, we see 42.82% improvement in energy delay product over the base case.

Optimizing Graph Algorithms in Asymmetric Multicore Processors

Deep Neural Networks (DNN) are used in a variety of applications and services. With the evolving nature of DNNs, the race to build optimal hardware (both in datacenter and edge) continues. General purpose multi-core CPUs offer unique attractive advantages for DNN inference at both datacenter [60] and edge [71]. Most of the CPU pipeline design complexity is targeted towards optimizing general-purpose single thread performance, and is overkill for relatively simpler, but still hugely important, data parallel DNN inference workloads. Addressing this disparity efficiently can enable both raw performance scaling and overall performance/Watt improvements for multi-core CPU DNN inference. We present REDUCT, where we build innovative solutions that bypass traditional CPU resources which impact DNN inference power and limit its performance. Fundamentally, REDUCT's "Keep it close" policy enables consecutive pieces of work to be executed close to each other. REDUCT enables instruction delivery/decode close to execution and instruction execution close to data. Simple ISA extensions encode the fixed-iteration count loop-y workload behavior enabling an effective bypass of many power-hungry front-end stages of the wide Out-of-Order (OoO) CPU pipeline. Per core performance scales efficiently by distributing lightweight tensor compute near all caches in a multi-level cache hierarchy. This maximizes the cumulative utilization of the existing architectural bandwidth resources in the system and minimizes movement of data. Across a number of DNN models, REDUCT achieves a 2.3X increase in convolution performance/Watt with a 2X to 3.94X scaling in raw performance. Similarly, REDUCT achieves a 1.8X increase in inner-product performance/Watt with 2.8X scaling in performance. REDUCT performance/power scaling is achieved with no increase to cache capacity or bandwidth and a mere 2.63% increase in area. Crucially, REDUCT operates entirely within the CPU programming and memory model, simplifying software development, while achieving performance similar to or better than state-of-the-art Domain Specific Accelerators (DSA) for DNN inference, providing fresh design choices in the AI era.

REDUCT: keep it close, keep it cool!: efficient scaling of DNN inference on multi-core CPUs with near-cache compute

Heterogeneous Multiprocessors (HMPs) are popular due to their energy efficiency over Symmetric Multicore Processors (SMPs). Asymmetric Multicore Processors (AMPs) are a special case of HMPs where different kinds of cores share the same instruction set, but offer different power-performance trade-offs. Due to the computational-power difference between these cores, finding an optimal hardware configuration for executing a given parallel program is quite challenging. An inherent difficulty in this problem stems from the fact that the original program is written for SMPs. This challenge is exacerbated by the interplay of several configuration parameters that are allowed to be changed in AMPs. In this work, we propose a probabilistic method named $\mathsf{CHOAMP}$ to choose the best available hardware configuration for a given parallel program. Selection of a configuration is guided by a user-provided run-time property such as energy-delay-product (EDP) and $\mathsf{CHOAMP}$ aspires to optimize the property in choosing a configuration. The core part of our probabilistic method relies on identifying the behavior of various program constructs in different classes of CPU cores in the AMP, and how it influences the cost function of choice. We implement the proposed technique in a compiler which automatically transforms a code optimized for SMP to run efficiently over an AMP, eliding requirement of any user annotations. $\mathsf{CHOAMP}$ transforms the same source program for different hardware configurations based on different user requirement. We evaluate the efficiency of our method for three different run-time properties: execution time, energy consumption, and EDP, in NAS Parallel Benchmarks for OpenMP. Our experimental evaluation shows that $\mathsf{CHOAMP}$ achieves an average of 65, 28, and 57 percent improvement over baseline HMP scheduling while optimizing for energy, execution time, and EDP, respectively.

$\mathsf{CHOAMP}$ : Cost Based Hardware Optimization for Asymmetric Multicore Processors

In this chapter, we describe Fast-SL, an in silico approach to predict synthetic lethals in genome-scale metabolic models. Synthetic lethals are sets of genes or reactions where only the simultaneous removal of all genes or reactions in the set abolishes growth of an organism. In silico approaches to predict synthetic lethals are based on Flux Balance Analysis (FBA), a popular constraint-based analysis method based on linear programming. FBA has been shown to accurately predict the viability of various genome-scale metabolic models. Fast-SL builds on the framework of FBA and enables the prediction of synthetic lethal reactions or genes in different organisms, under various environmental conditions. Predicting synthetic lethals in metabolic network models allows us to generate hypotheses on possible novel genetic interactions and potential candidates for combinatorial therapy, in case of pathogenic organisms. We here summarize the Fast-SL approach for analyzing metabolic networks and detail the procedure to predict synthetic lethals in any given metabolic model. We illustrate the approach by predicting synthetic lethals in Escherichia coli. The Fast-SL implementation for MATLAB is available from https://github.com/RamanLab/FastSL/ .

Computational Prediction of Synthetic Lethals in Genome-Scale Metabolic Models Using Fast-SL.

Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for DNN inference along with mature high performance libraries to extract optimal performance. While general purpose CPUs offer unique attractive advantages for DNN inference at both datacenter and edge, they have primarily evolved to optimize single thread performance. For highly parallel, throughput-oriented DNN inference, this results in inefficiencies in both power and performance, impacting both raw performance scaling and overall performance/watt. 
We present Proximu$\$$, where we systematically tackle the root inefficiencies in power and performance scaling for CPU DNN inference. Performance scales efficiently by distributing light-weight tensor compute near all caches in a multi-level cache hierarchy. This maximizes the cumulative utilization of the existing bandwidth resources in the system and minimizes movement of data. Power is drastically reduced through simple ISA extensions that encode the structured, loop-y workload behavior. This enables a bulk offload of pre-decoded work, with loop unrolling in the light-weight near-cache units, effectively bypassing the power-hungry stages of the wide Out-of-Order (OOO) CPU pipeline. 
Across a number of DNN models, Proximu$\$$ achieves a 2.3x increase in convolution performance/watt with a 2x to 3.94x scaling in raw performance. Similarly, Proximu$\$$ achieves a 1.8x increase in inner-product performance/watt with 2.8x scaling in performance. With no changes to the programming model, no increase in cache capacity or bandwidth and minimal additional hardware, Proximu$\$$ enables unprecedented CPU efficiency gains while achieving similar performance to state-of-the-art Domain Specific Accelerators (DSA) for DNN inference in this AI era.

Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute.

Implementations of the disclosure implement timely and context triggered (TACT) prefetching that targets particular load IPs in a program contributing to a threshold amount of the long latency accesses. A processing device comprising an execution unit; and a prefetcher circuit communicably coupled to the execution unit is provided. The prefetcher circuit is to detect a memory request for a target instruction pointer (IP) in a program to be executed by the execution unit. A trigger IP is identified to initiate a prefetch operation of memory data for the target IP. Thereupon, an association is determined between memory addresses of the trigger IP and the target IP. The association comprising a series of offsets representing a path between the trigger IP and an instance of the target IP in memory. Based on the association, an offset from the memory address of the trigger IP to prefetch the memory data is produced.

Shankar Balachandran

Papers

REDUCT: keep it close, keep it cool!: efficient scaling of DNN inference on multi-core CPUs with near-cache compute

$\mathsf{CHOAMP}$ : Cost Based Hardware Optimization for Asymmetric Multicore Processors

Computational Prediction of Synthetic Lethals in Genome-Scale Metabolic Models Using Fast-SL.

Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute.

Supporting timely and context triggered prefetching in microprocessors