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Sharon Hu

Researcher at University of Notre Dame

Publications -  13
Citations -  639

Sharon Hu is an academic researcher from University of Notre Dame. The author has contributed to research in topics: Quantum dot cellular automaton & Authentication. The author has an hindex of 7, co-authored 13 publications receiving 473 citations.

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Journal ArticleDOI

Scaling for edge inference of deep neural networks

TL;DR: There are increasing gaps between the computational complexity and energy efficiency required for the continued scaling of deep neural networks and the hardware capacity actually available with current CMOS technology scaling, in situations where edge inference is required.
Proceedings ArticleDOI

Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation

TL;DR: This paper applies quantization techniques to FCNs for accurate biomedical image segmentation with a focus on a state-of-the-art segmentation framework, suggestive annotation, which judiciously extracts representative annotation samples from the original training dataset, obtaining an effective small-sized balanced training dataset.
Journal ArticleDOI

Searching for multiobjective preventive maintenance schedules: Combining preferences with evolutionary algorithms

TL;DR: This paper uses evolutionary algorithms to solve the multiobjective problem of scheduling preventive maintenance tasks at aircraft service centers or railroad yards, rather than conducting a conventional dominance-based Pareto search, and introduces a form of utility theory to find Pare to optimal solutions.
Posted Content

Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation

TL;DR: In this paper, the authors apply quantization techniques to fully convolutional networks (FCNs) for biomedical image segmentation, which can reduce memory and computation complexity of DNNs while maintaining acceptable accuracy.
Proceedings ArticleDOI

A cost-effective tag design for memory data authentication in embedded systems

TL;DR: The proposed tag design approach can produce a memory data protection design with a low resource cost - achieving overhead savings of about 39% on chip area, 45% on power consumption, 65% on performance, and 12% on memory cost while maintaining the same or higher security level.