An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Method of fabricating an high-performance insulated-gate field-effect transistor

A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Method of fabricating a raised source/drain transistor

A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.

Semiconductor device and process for manufacturing the same

High-performance insulated-gate field-effect transistor

An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region. The only lithography step needed in this portion of the process is one to protect the dopant source layer over the second region while sidewall spacers are being formed in the first region.

CMOS process using doped glass layer

A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer. The silicide region over each of the well regions is doped with a conductivity modifier of a conductivity type opposite that of the well region. The device is then heated to diffuse the conductivity modifiers through the polycrystalline silicon layer into the silicon body to form shallow source and drain regions in each well at each side of the gate lines.

Sheng T. Hsu

Papers

Method of making cmos with shallow source and drain junctions