An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.

SOI DRAM having P-doped poly gate for a memory pass transistor

PURPOSE:To provide a connecting device having a contact terminal which making contact with a subject to be inspected in multipoint with high density, and a method for manufacturing this device. CONSTITUTION:A silicon wafer is anisotropically etched with a silicon dioxide film as a mask to form a projection for forming a contact terminal 42, and the silicon dioxide film around this projection is anisotropically etched in U- shape, whereby a cantilever beam having the projection is formed, and the contact terminal 42 and a lead-out wiring 40 are formed by use of conductive coating. Further, a buffer layer 46 is nipped between a silicon wafer 28 having the contact terminal 42 formed thereon and a wiring base 70, and integrated thereto. Thereafter, a drawing wiring 72 is connected to the electrode 73 of the wiring base 70.

Connecting device and its manufacture

An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

Programmable logic device

A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

Programmable circuit and related computing machine, and method

One main surface of a substrate has formed on it an appropriate contact terminal having in one part thereof a protruding part. An end of a lead is mounted via a holding part that is provided between the substrate and a probe, the lead being disposed along the main surface of the substrate so as to peel away from the main surface.

Probe card and method of forming a probe card

PROBLEM TO BE SOLVED: To obtain a programmable logical device which can realize an inexpensive board system by decreasing the number of logical gates per unit area. SOLUTION: A logical block 1 capable of implementing various logical functions, programmable wiring 2 capable of altering the connection state, and a programmable I/O block 3 capable of altering the I/O state are provided with ferroelectric memories 4, 5 and 6 for storing configuration information defining the operation thereof. A plurality of pieces of configuration information are stored in each ferroelectric memory 4, 5, 6 and an information selecting means 7, 8, 9 selects an arbitrary one. The number of logical gates can be substantially increased by using the plurality of pieces of configuration information while switching and an inexpensive board system can be realized because no extra nonvolatile memory is required externally. COPYRIGHT: (C)2003,JPO

Programmable logical device

PROBLEM TO BE SOLVED: To more prolong the communication distance of a battery less RFID. SOLUTION: An oscillation circuit 16 is constituted so as to output a machine clock signal MCLK of frequency obtained by dividing the frequency of a clock signal FSKCLK into two halves when a clock selection signal CLKSEL is an 'H' level and output a machine clock signal MCLK of frequency obtained by dividing the frequency of the clock signal FSKCLK into four frequency components when the clock selection signal CLKSEL is an 'L' level. When the clock selection signal CLKSEL is set up in the circuit 16 so as to reduce the frequency of the machine clock signal MCLK for a CPU 21, a ROM 22 and an EEPROM 23 at the time of data transmission using a PSK circuit 15, power consumption to be used for operation other than transmitting operation is suppressed to a low level and more power can be allocated to the data transmission of the PSK circuit 15, so that the communication of longer distance can be attained.

Battery less rfid

PROBLEM TO BE SOLVED: To simplify design, and to reduce electric power consumption in an information processor for receiving a carrier wave modulated according to prescribed information, and executing prescribed processing by extracting information and electric power. SOLUTION: A receiving means 1b receives the carrier wave from a reader writer 2. A DC power generating means 1c generates DC power by rectifying the carrier wave received by the receiving means 1b. A demodulating means 1d is constituted independently of the DC power generating means 1c, and demodulates the information superimposed on the carrier wave. An information processing means 1e executes the prescribed processing on the information demodulated by the demodulating means 1d with DC power generated by the DC power generating means 1c as a power source. Thus, since the demodulating means 1d and the DC power generating means 1c are independently constituted, mutual interference between elements included in respective circuits can be excluded, the design can be simplified, and the electric power consumption of the circuits can be reduced by optimal design.

Information processor and card type information processing device

PURPOSE: To reduce the contact resistance between a metal layer on a probe card and a metal for electrode on an integrated circuit to be measured, in a probe card made by utilizing a silicon wafer among probe cards utilized for the test of a semiconductor integrated circuit in the wafer condition. CONSTITUTION: A silicon wafer 1 is a supporting body in a probe card. Metal layers 4 to be pressed against the metal pads of elements to be measured (DUT) are prepared by the number of the metal pads on the DUT required for measuring. A transparent insulating membrane 3 is used for holding the metal layer 4, for sealing so as not to leak when air pressure is impressed from the over side of the silicon wafer, for observing the position of the metal pad on the DUT from the upper side of the probe card, and for being an stopping layer to etch when the silicon wafer as the supporting body is treated with anisotropic etching. COPYRIGHT: (C)1994,JPO&Japio

Probe card utilizing silicon wafer

PROBLEM TO BE SOLVED: To exactly reproduce the stored data in a ferroelectric capacitor used in a programmable logic device when the power is turned on, improve the reliability of the stored data in ferroelectric SRAM cells, composed of SRAM memory cells with the ferroelectric capacitors attached thereto, and quickly start logic operations after power is turned on. SOLUTION: When the power is turned on, a configuration memory 23 is fed with an externally supplied power voltage Vdd with a delay, depending on the time constant according to the characteristics of a ferroelectric capacitor. The drop in the externally supplied power voltage Vdd is detected to fully apply the power voltage to ferroelectric SRAM cells, and then its power source is cut off. Information whether configuration information are already written or not are held in the ferroelectric SRAM cells. If not yet written or already written, the output of a logic block is forcibly disabled or enabled, respectively. COPYRIGHT: (C)2003,JPO

昇一桝井

Papers

Programmable logical device

Battery less rfid

Information processor and card type information processing device

Probe card utilizing silicon wafer

Programmable logic device, non-volatile memory and data reproducing method

昇一 桝井

Papers

Programmable logical device

Battery less rfid

Information processor and card type information processing device

Probe card utilizing silicon wafer

Programmable logic device, non-volatile memory and data reproducing method

昇一桝井