The growing maturity of integrated photonic technology makes it possible to build increasingly large and complex photonic circuits on the surface of a chip. Today, most of these circuits are designed for a specific application, but the increase in complexity has introduced a generation of photonic circuits that can be programmed using software for a wide variety of functions through a mesh of on-chip waveguides, tunable beam couplers and optical phase shifters. Here we discuss the state of this emerging technology, including recent developments in photonic building blocks and circuit architectures, as well as electronic control and programming strategies. We cover possible applications in linear matrix operations, quantum information processing and microwave photonics, and examine how these generic chips can accelerate the development of future photonic circuits by providing a higher-level platform for prototyping novel optical functionalities without the need for custom chip fabrication. The current state of programmable photonic integrated circuits is discussed, including recent developments in their building blocks, circuit architectures, electronic control and programming strategies, as well as different application spaces.

https://biblio.ugent.be/publication/8677857/file/8677861.pdf

Programmable photonic circuits.

Silicon Photonics technology is rapidly maturing as a platform for larger-scale photonic circuits. As a result, the associated design methodologies are also evolving from componentoriented design to a more circuit-oriented design flow, that makes abstraction from the very detailed geometry and enables design on a larger scale. In this paper, we review the state of this emerging photonic circuit design flow and its synergies with electronic design automation (EDA). We cover the design flow from schematic capture, circuit simulation, layout and verification. We discuss the similarities and the differences between photonic and electronic design, and the challenges and opportunities that present themselves in the new photonic design landscape, such as variability analysis, photonic-electronic co-simulation and compact model definition. Silicon Photonics Circuit Design: Methods, Tools and

https://www.onlinelibrary.wiley.com/doi/epdf/10.1002/lpor.201700237

Silicon Photonics Circuit Design: Methods, Tools and Challenges

Photonic switches are increasingly considered for insertion in high performance datacenter architectures to meet the growing performance demands of interconnection networks. We provide an overview of photonic switching technologies and develop an evaluation methodology for assessing their potential impact on datacenter performance. We begin with a review of three categories of optical switches, namely, free-space switches, III-V integrated switches and silicon integrated switches. The state-of-the-art of MEMS, LCOS, SOA, MZI and MRR switching technologies are covered, together with insights on their performance limitations and scalability considerations. The performance metrics that are required for optical switches to truly emerge in datacenters are discussed and summarized, with special focus on the switching time, cost, power consumption, scalability and optical power penalty. Furthermore, the Pareto front of the switch metric space is analyzed. Finally, we propose a hybrid integrated switch fabric design using the III-V/Si wafer bonding technique and investigate its potential impact on realizing reduced cost and power penalty.

Photonic switching in high performance datacenters [Invited]

Fast optical switches have been proposed as a promising alternative to enable continual scaling of data centers with increasing size and data rates. Silicon photonics is a compelling platform for large-scale integrated photonic switches, leveraging advanced manufacturing foundries for electronic integrated circuits. In the past decade, the port counts of silicon photonic switches have increased steadily to 128×128. Further scaling of the switch is constrained by the maximum reticle size (2–3 cm) of lithography tools. Here, we propose to use wafer-scale integration to overcome the die size limit. As a proof of concept demonstration, we fabricated a 240×240 switch by lithographically stitching a 3×3 array of identical 80×80 switch blocks across reticle boundaries. Stitching loss is substantially reduced (0.004 dB) by tapering the waveguide width to 10 μm. The fabricated switch on a 4 cm×4 cm chip exhibits a maximum on-chip loss of 9.8 dB, an ON/OFF ratio of 70 dB, and switching times of less than 400 ns. To our knowledge, this is the largest integrated photonic switch ever reported. The loss-to-port count ratio (0.04 dB/port) is also the lowest.

Wafer-scale silicon photonic switches beyond die size limit

Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts toward reaping their benefits while avoiding technology limitations on the way to manycore set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than four interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically-enabled eight-socket boards can be combined via a 256 × 256 Hipoλaos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a mean to increase the number of synergized high-performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off-die ultrafast optical cache memory chiplets.

/pdf/optics-in-computing-from-photonic-network-on-chip-to-chip-to-4ydunis18y.pdf

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

A packaged and fully operational 32 × 32 silicon photonic switch chip having 448 switch cells and 1856 crossings is demonstrated. The switch chip includes 900 monolithically integrated photodiodes used for calibrating the thermo-optic Mach–Zehnder switch cells. The calibration procedure employs an external laser source and follows a reachability-tree sequence to calibrate all switch cells. The accuracy of the calibration is demonstrated by the measurement of switch cell extinction ratios, for both states of each switch cell. The mean extinction ratio for both states is 35 dB. Arbitrary light path switching is demonstrated. Measurement of the channel-to-channel crosstalk was performed for a large number of aggressor and victim light path combinations. The matrix crosstalk is dominated by contributions from waveguide crossings. The die was wire-bonded to a custom ceramic package, to which a 68-fiber ribbon was permanently attached, which coupled the input and output optical signals to edge couplers on the chip through a waveguide pitch- and mode-concentrating silica chip. The fiber-to-fiber loss of on-chip loopback waveguides was less than 6.5 dB from 1530 to 1565 nm. The entirety of switch cells and monitors was driven by controller boards and A/D chips using a controller field-programmable gate array (FPGA). The calibration procedure was completed in less than 10 min using only the on-chip monitors, without off-chip detectors. The chip was recalibrated after six months storage, and the measured change in drive current was within the calibration uncertainty, indicating that the chip and driver are stable over time.

Silicon Photonic Switch Subsystem With 900 Monolithically Integrated Calibration Photodiodes and 64-Fiber Package

Lightpaths are switched in a 32×32 silicon photonic switch, with 448 thermo-optic Mach-Zehnders and 864 monolithic monitor photodiodes. It is packaged in a CBGA with 68-fiber ribbon, and every cell has an off-chip control circuit.

32×32 silicon photonic switch

Monolithic germanium photodiodes on every cell calibrate a 32×32 silicon photonic switch of 448 Mach-Zehnders in 10 minutes. 64 fibers permanently attached through a waveguide concentrator in a wire-bonded BGA achieve 2.9dB C-band TE fiber-to-die.

Silicon photonic switch subsystem with 900 monolithically integrated calibration photodiodes and 64-fiber package

A packaged and fully operational 32×32 silicon photonic switch chip having 448 switch cells and 1856 crossings is demonstrated. Development of low loss optical components is essential to the operation of complex Mach-Zehnder switch fabrics.

Large-Scale Silicon Photonic Switch

We implement a silicon photonic 16-port add-or-drop, with on-chip polarization diversity including polarization splitter rotators and dual switch cores. PDL, DGD of express and add were 0.3dB, <0.1ps and 1.1dB, <3ps respectively. 200Gb/s and 400Gb/s PDM-16QAM signals were transmitted, with 0.1dB ROSNR penalty at 200Gb/s.

Shengyong Yan

Papers

Silicon Photonic Switch Subsystem With 900 Monolithically Integrated Calibration Photodiodes and 64-Fiber Package

32×32 silicon photonic switch

Silicon photonic switch subsystem with 900 monolithically integrated calibration photodiodes and 64-fiber package

Large-Scale Silicon Photonic Switch

Dual-core polarization diverse silicon photonic add/drop switch supporting 400Gb/s PDM-16QAM