An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.

Electronic device and method of manufacturing the same, circuit board, and electronic instrument

A method and apparatus for annealing copper. The method comprises forming a copper layer by electroplating on a substrate in an integrated processing system and annealing the copper layer in a chamber inside the integrated processing system.

Method and apparatus for annealing copper films

This invention provides a lead-free high temperature solder material comprising 0005-30 wt % of palladium (Pd) and 970-99995 wt % of tin (Sn) whose liquidus temperature is 200-350° C The solder material is environmentally-friendly, improved in thermal fatigue property, and it can improve the reliability of electronic apparatuses A predetermined amount of Sn material and Pd is mixed, vacuum-melted and cast to prepare an ingot The ingot is rolled to be a tape that is later pressed to obtain a solder pellet In a preferable composition, at least 95 wt % of Sn and 0005-30 wt 5 of Pd are contained, and 01-50 wt % of metallic (eg Cu, Ni) or alloy particles are added The average particle diameter is about 40 μm A substrate and an IC chip (electronic element) are die-bonded substantially in parallel by a solder material provided between an Ni plating on the lower side of an IC chip (semiconductor) and an Ni plating on a die

Solder material and electronic part using the same

A brazing filler metal is composed of gold, silver, copper, and an additive element including at least one kind of element out of aluminum, bismuth, gallium, germanium, indium, antimony, silicon, tin, lead, tellurium, and thallium, as main constituents thereof, wherein a total composition ratio of the additive element is in a range of more than 1 wt. % to less than 36 wt. %, and a composition ratio of the gold is less than 80 wt. %, and a composition ratio of the silver is less than 42 wt. %, so that the brazing filler metal joins metals for use as members of which decorativeness in external appearance is required, such as stainless steel and so on, at a low temperature which does not cause the crystal structure thereof to be coarsened, while securing excellent corrosion resistance and sufficient joining strength.

Brazing filler metal

A high solidus temperature, high service temperature, high strength ternary solder alloy, solder paste and method. The alloy contains a major proportion of tin of at least about 70 % by weight, a selectively limited amount of silver from about 6.5 to about 7.5 % by weight, balance indium.

Lead-free, high tin ternary solder alloy of tin, silver, and indium

PROBLEM TO BE SOLVED: To form plating layers having a high bonding property without using Ni-P plating by plating Ni-B of a specific thickness as ground surface plating on the soldering parts and bonding parts of semiconductors and electronic parts and plating Pd thereon at a specific thickness. SOLUTION: The Ni-B plating contg. 0.01 to 10% B is first formed at a thickness of 0.01 to 20 μm on the soldering parts and wire bonding parts of the electronic parts, such as semiconductor elements and lead frames. The Pd is then plated at a thickness of 0.005 to 10 μm thereon and further, in some cases, Au is plated in superposing thereon at a thickness of 0.005 to 5 μm. The plating having a good bonding property, such as the excellent resistivity to solder erosion, good wettability of deposited metal, high strength of adhesion, excellent heat resistance, etc., may be formed without applying the Ni-P which is used thus far as the ground surface plating and has defects. The quality and the reliability of semiconductors and electronic parts are improved.

Plating structure of bonding part

PROBLEM TO BE SOLVED: To prevent variations of thickness of aluminum electrode formed on a semiconductor chip and variations of height of the electrode when a bump, etc., are formed on the aluminum electrode. SOLUTION: In this method, an aluminum layer 4 and an electrode part 100a comprising a metallic layer 20 which is nobler than aluminum, laminated on the aluminum layer 4 are formed on a semiconductor substrate 2 comprising a semiconductor chip 1. In this case, the aluminum layer 4 is formed on the whole surface of the semiconductor substrate 2. A metallic layer which is nobler than aluminum is laminated on the part to be at least electrode part on the aluminum layer 4 without previously patterning the aluminum layer 4 on an electrode pattern. As a result, an electrode pattern 30 having laminated structure of the aluminum layer 4 and the metallic layer 20 which is noble than aluminum is formed. Subsequently, a protective film 7 is formed in such a way as to open the electrode pattern 30. Furthermore, if necessary, a bump is formed.

Method for producing electrode part of semiconductor chip

PURPOSE: To remarkably improve solderability of I/O terminals of a semiconductor chip, adhesion to a board, and bonding quality, directly mount a semiconductor chip on the board by wireless bonding without forming solder bumps, and in particular, mount a semiconductor chip on a board with high adhesion in a repair process. CONSTITUTION: The I/O terminal of a semiconductor chip is constituted of a base material metal layer 2 like aluminum, and a nickel alloy thin layer 3 and a noble metal thin layer 4 which are laminated in order on the layer 2. As the nickel alloy thin layer 3, an alloy layer wherein Ni is used as the main component, and at least one kind out of Cu, Mn, Mg, Cr Si, W, Au, Ti and V is contained is formed by electroless plating. After the nickel alloy thin layer 3 and the noble metal thin layer 4 are laminated on the base material metal layer 2 of the I/O terminal, the interfacial adhesion of layers is improved by heat treatment. COPYRIGHT: (C)1996,JPO

Semiconductor chip, forming method of semiconductor chip terminal, and bonding method of semiconductor chips

When an electronic component and a wiring board are connected to each other by soldering, the present invention uses, as an alloy to be plated, an alloy containing 0.01 to 90 wt% of palladium in lead, tin or their alloy as a thin film to be formed on a to-be-plated portion of the electronic component or the wiring board so as to effectively carry out the connection. Particularly preferred is an alloy containing 0.1 to 70 wt% of lead, 0.1 to 90 wt% of tin and 0.01 to 90 wt% of palladium. Furthermore, when this alloy further contains 0.1 to 20 wt% of phosphorus or 0.01 to 10 wt% of boron, the drop of solderability of the alloy due to heat can be much more reduced. When 0.1 to 20 wt% of indium is contained, the melting point of the alloy can be lowered and when 0.1 to 20 wt% of silver is contained, leaching can be reduced. This alloy to be plated is preferably formed on the to-be-plated portion by electrolytic or electroless plating by the use of a plating solution for the alloy to be plated which contains 0.001 to 2 mols/l of a palladium compound, 0.001 to 3 mols/l of a tin compound and or 0.001 to 2 mols/l of a lead compound. In the case of electroless plating, it is preferred to use a plating solution additionally containing 0.01 to 1 mol/l of a reducing agent.

Shigeaki Ueda

Papers

Plating structure of bonding part

Method for producing electrode part of semiconductor chip

Semiconductor chip, forming method of semiconductor chip terminal, and bonding method of semiconductor chips

Alloy to be plated, its plating method and plating solution