Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

A physiological monitoring garment (10) includes first and second elastic fabric portions (12, 14). An elongate stretchable textile data/power bus (16) is disposed between the first and second elastic fabric portions (12, 14). The elongate stretchable textile data/power bus (16) includes a plurality of integral conductors (20), woven, knitted, or braided along the length thereof. One or more sensors (30, 32) are connected to the elongate stretchable textile data/power bus (16).

Physiological monitoring garment

A disclosed gaming machine provides a plurality of virtual gaming peripherals that are each used to generate one or more gaming services. To provide a particular gaming service, each virtual gaming peripheral may comprise virtual gaming peripheral software that controls one or more gaming devices. Examples of gaming services provides by virtual gaming peripherals may include but are not limited to a player tracking service, a vending machine purchase, a lottery ticket purchase, an ATM (Automatic Teller Machine) service, a hotel/casino service, a communication service, a registration service, a sports book service, an entertainment service, a prize redemption service and a locator service. A logic device, such as a master gaming controller on the gaming machine, may simultaneously activate a plurality of virtual gaming peripherals. Therefore, a gaming device may be shared by a plurality of active virtual gaming peripherals and additional logic may be provided to resolve conflicts that arise when two or more virtual gaming peripherals desire to control the same gaming device at the same time.

Virtual gaming peripherals for a gaming machine

Various gaming-related services are provided, including but not limited to security services, harm minimization services, player identification services, bonusing/progressive services, accounting services, financial/banking services, network tunneling services, cheating detection services, etc. Such services may be provided, at least in part, by software agents that can be configured for different platforms and/or operating systems. Some software-based player tracking methods of the invention can aggregate data from multiple devices used by a player for gaming.

Virtual player tracking and related services

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

Protocol for communication with dynamic memory

A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor

A synchronous semiconductor memory device includes a clock input circuit receiving an externally applied clock signal to produce an internal clock signal, a signal input circuit taking in an externally applied signal to produce an internal signal, a first delay circuit delaying an externally applied snooze mode signal by a first delay time for supplying to a clock input circuit, and a second delay circuit delaying the externally applied snooze mode signal by a second delay time for supplying to the signal input circuit. The clock input circuit and the signal input circuit are disabled when the internal snooze mode signal is active. The semiconductor memory device takes in the external signal and produces an internal signal in synchronization with the internal clock signal. Upon switching over to the snooze mode, the operation is performed in accordance with the external signal in the cycle in which the snooze mode is designated, and the internal operation is inhibited in the subsequent cycles. Upon release from the snooze mode, the internal clock signal is produced in the cycle subsequent to the cycle in which the release from the snooze mode is designated, and the signal input circuit is enable in and after the clock cycles subsequent to the cycle in which the internal clock signal is produced.

Synchronous semiconductor memory device operable in a snooze mode

In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

Power on reset circuit

In a test operation for a semiconductor memory device, memory power supply lines are disconnected from a power supply node by using switch gates. Voltages of the memory power supply lines are detected using detection holding circuits. When the detected voltage is lower than a predetermined value, the corresponding memory power supply line is driven to a ground voltage level by the detection holding circuit. Thereby, a standby-current-defective but normally-operable memory cell is forced to an operation-defective state. Then, the standby-current-defective memory cell is identified, and redundancy replacement is performed thereon. Consequently, the standby current abnormality in the semiconductor memory device can be repaired.

Semiconductor memory device and testing method therefor

A synchronous semiconductor memory device includes a clock pulse generator generating internal first and second clock pulses in synchronization with an external clock signal for application, respectively, to a word line select decoder selecting a row of memory cells, and to a bit line select decoder selecting a column of memory cells, a sense amplifier sensing and amplifying a data of selected memory cell and a write driver writing a data to the selected memory cell. Word line select decoder is enabled when the first clock pulse is active, and bit line select decoder, sense amplifier and write driver are activated when the second clock pulse is active. These circuits are activated only for a necessary minimum period, and current consumption is reduced.

Shigeki Ohbayashi

Papers

Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor

Synchronous semiconductor memory device operable in a snooze mode

Power on reset circuit

Semiconductor memory device and testing method therefor

Clock synchronous semiconductor memory device having current consumption reduced