The main concept of type-2 fuzzy logic is that "words mean different things to different people"; thus, there are uncertainties associated with words. Recently, a lot of mathematical theorems have been developed for type-2 fuzzy logic. However, to the best of our knowledge, there has been no hardware implementation. In this paper, we propose the first hardware architecture to support the type-2 fuzzy inference execution. Moreover, we also use a 0.35/spl mu/m cell library to implement the proposed architecture. Implementation data show that the inference speed reaches 3.125 MFLIPS with 2 inputs, 1output and 64 rules.

VLSI implementation of type-2 fuzzy inference processor

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree MD between the fuzzified input and the antecedent membership functions MF has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MF's, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.

A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

The hardware design of a fuzzy processor is always intended to improve its inference performance for real time applications or to reduce the overall cost. The applications of fuzzy logic in various fields have always suffered from a major problem of low speed of operation. The calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture for calculating the matching between two triangular-shaped membership functions has been proposed. The VHDL implementation of the proposed architecture has been performed. The proposed architecture is more efficient in area and the speed of operation in comparison to a more complex architecture used for the trapezoid-shaped membership function. The proposed architecture has been implemented in a Xilinx Field Programmable Gate Array (FPGA). Further, from the proposed architecture, matching of other type of membership functions can also be obtained easily.

Architectural design of fuzzy inference processor using triangular-shaped membership function

The most obvious architectural solution for high-speed fuzzy inference is to exploit the temporal parallelism and spatial parallelism inherited in a fuzzy inference execution. However, the active rules in a fuzzy inference execution are often only a small part of the total rules. In this paper, we present a new architecture, which uses less hardware resources by discarding non-active rules in the earlier pipeline stage. Implementation data demonstrates that the proposed architecture achieves very good results in terms of the inference speed and the chip area.

A high speed fuzzy inference processor with dynamic analysis and scheduling capabilities

In this paper, a fast fuzzy controller which is implemented in an FPGA chip is used for the position control of DC motor. The technique of parallel architecture, direct computation and combinational circuit is adopted for the design of controller. In order to simplify the operation of input firing, we adopt the triangular membership function as the fuzzy sets for antecedent part. The firing strength of those triggered fuzzy rules are calculated through the parallel processing, when dealing with the fuzzy inference. For the consequent part of the fuzzy rule, the design parameters are stored as a ROM table so that it can be easily achieved for fuzzy inference. Meantime, a special divider circuit structure is proposed so that only one clock computation time is required for the operation of division. Then, the center average method is used to construct the defuzzifier. In order to demonstrate the correctness and efficiency of the proposed fuzzy control circuit, we combine the fuzzy controller with feedback circuit, comparison circuit as well as driving circuit and implement the whole controller in a Xilinx Spartan 3 FPGA chip. The digital fuzzy controller is applied to the position tracking control of DC motors. The simulation and experimental results show that the presented fuzzy control circuit is feasible.

Design of fast fuzzy controller and its application on position control of DC motor

We present a high-speed VLSI fuzzy logic controller, which is well suitable for real time applications. The main distinction of our approach is that it may complete the max-min calculation within one clock cycle. The speedup is achieved by an effective format for membership function and a careful analysis to the conditions of max-min calculation. As a result, the latency of a fuzzy inference can be considerably reduced. Based on the basic idea, a pipelined parallel architecture is proposed to fully utilize the parallelism inherited in the fuzzy inference. The VLSI fuzzy logic controller was implemented and simulated by using 0.35 /spl mu/m cell library as the target technology. Experimental data shows that the proposed architecture achieves higher performance compared with other approaches.

Shih-Hsu Huang

Papers

A high-speed VLSI fuzzy logic controller with pipeline architecture