A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal silicide film on the whole surface of the resulting structure, and patterning the resulting structure, and forming source and drain regions, by implanting ions by using the gate electrodes as an ion implant mask.

Method of manufacturing flash memory device

A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830° C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000. After the formation of the high voltage gate oxide (34), a lower voltage logic gate oxide (36) is then formed.

Method for forming a high voltage gate dielectric for use in integrated circuit

A method for depositing a high-k dielelectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate.

Method of forming dielectric films

A method for making gate dielectrics for MOS devices includes first forming a silicon oxynitride layer, and then forming a silicon dioxide layer that underlies the oxynitride layer. The oxynitride layer functions as a membrane for controlled diffusion of oxygen to the oxidation region of the silicon substrate.

Oxynitride-dioxide composite gate dielectric process for MOS manufacture

A semiconductor structure is provided having an improved oxide with minimal irregularities and charge trap densities. The oxide is formed by an oxidation process which controls temperature and ambient conditions during oxidation as well as prior to and after oxidation. The ambient conditions are chosen such that the silicon surface is more receptive to growing a high quality, relatively thin oxide. A post-oxidation anneal helps ensure any irregularities, dislocations, contaminants involved in trap formation are minimized after the oxide is grown. A post-oxidation anneal involving oxygen incorporated into the oxide is presumed to help minimize any defects which might result from the pre-existing oxidation cycle. A slow ramping of temperature and close control of that temperature helps minimize trap locations at or near the silicon surface on which oxide will be grown. The combination of pre- and post-oxidation anneal, the ambient chosen, and various cleaning(g steps prior to oxidation helps ensure a high quality gate or tunnel oxide of relatively thin dimension.

Fabrication sequence employing an oxide formed with minimized inducted charge and/or maximized breakdown voltage

A fabrication method of a semiconductor device is disclosed Particularly, in the process of forming a gate oxide film on a semiconductor substrate, the method for forming a gate oxide film of a semiconductor device comprises the steps of first-annealing the semiconductor substrate in a nitrogen (N2) atmosphere; forming a gate oxide film by wet-oxidizing the annealed semiconductor substrate at a low temperature in a mixed gas atmosphere of oxygen (O2) and hydrogen (H2); and second-annealing the semiconductor substrate where gate oxide film has been formed, at a high temperature in a nitrogen (N2) atmosphere Accordingly, the thinning phenomenon of the gate oxide film near the field oxide film is prevented and the instability such VFB in the conventional field oxidation method is considerably recovered Also, the field concentration phenomenon is decreased and tolerance to dielectric breakdown is increased

Method for forming a gate oxide film of a semiconductor device

forming a field oxide for separating active layers; forming the first gate oxide on the active region of the substrate; depositing a photoresist layer for making the first MOS transistor; removing selectively the first gate oxide of the region for the second MOS tr.; removing the remaining PR and controlling the thickness of the first gate oxide by partial etching; finally forming the second gate oxide on the formed active areas and completing the usual fabrication process.

Shin Dong-Ho

Papers

Method for forming a gate oxide film of a semiconductor device

Semiconductor device and fabricating method thereof