At least one annular region (11,12, . . . ) extends around an active device region (10) and is located within the spread of a depletion layer (25) from a reverse-biased p-n junction (20) formed by the device region (10) to increase the breakdown voltage of the junction (20). The device region (10) and/or at least one inner annular region (11,12, . . . ) includes at least one shallower portion (10b,11b, . . . ) which extends laterally outwards from a deep portion (10a,11a,12a, . . . ) and faces the surrounding annular region to change the spacing and depth relationship of these regions. This permits high punch-through voltages to be achieved between the regions (10,11,12, . . . ) while reducing peak fields at the bottom outer corners of the regions (10,11,12, . . . ). Inwardly-extending shallow portions (11c,12c, . . . ) may also be included. The shallow portions (10b,11b,11c,12c . . . ) may extend around the whole of a perimeter of the region or be localized where higher electrostatic fields may occur around the perimeter.

High voltage guard ring with variable width shallow portion

In a semiconductor structure having two highly and similarly doped, e.g., P+ type, regions (26,30) embedded in close juxtaposition in a trench-isolated N type silicon mesa (22), N+ channel stops (40,42) embedded in the N type mesa between the P type regions, are provided. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. A process of forming such channel stops introduces N type dopant into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region.

Self-aligned channel stop

A two dimensional focal plane array of Schottky photodiodes on a silicon substrate for infrared imaging. The array is designed for mating with multiplexing circuitry and has a self-guarding feature wherein adjacent Schottky electrodes act as guard electrodes. This feature allows a substantial increase of the focal plane area coverage ratio.

Self-guarding Schottky barrier infrared detector array

A planar semiconductor device having a main p-n junction surrounded by at least one guard ring covered with an insulating layer having an opening is provided with an electrode electrically connected to said guard ring through the opening. The said electrode is provided such that it does not extend beyond the end of the guard ring region which is located in an opposite side to the main p-n junction.

Planar semiconductor device with dual conductivity insulating layers over guard rings

A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

Multiple junction thin film transistor

A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

Shinishi Saiki

Papers

Semiconductor device having at least one PN junction and channel stopper surrounder by a protecture conducting layer