S
Shinitsu Takehashi
Researcher at Panasonic
Publications - 17
Citations - 290
Shinitsu Takehashi is an academic researcher from Panasonic. The author has contributed to research in topics: Thin-film transistor & Liquid-crystal display. The author has an hindex of 8, co-authored 17 publications receiving 290 citations. Previous affiliations of Shinitsu Takehashi include Toshiba.
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Patent
Liquid crystal display device, electroluminescent display device, method of driving the devices, and method of evaluating subpixel arrangement patterns
TL;DR: In this paper, a pixel-dividing technique and a capacitively-coupled driving method are combined to achieve a gray-scale display based on a digital image signal.
Patent
Thin-film transistor, panel, and methods for producing them
TL;DR: In this article, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions.
Patent
Semiconductor device and method of producing said semiconductor device.
Shinitsu Takehashi,Kenzo Hatada +1 more
TL;DR: In this paper, a virtual octagon is formed by outward enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips (8a,b).
Patent
Method for bonding lead with electrode of electronic device
TL;DR: In this paper, a method for bonding leads of a film carrier to electrodes of electronic devices includes a step for positioning leads and the electrodes with a predetermined clearance aligned to define corresponding pairs of the leads and electrodes, and another step for placing a bonding tool having a conductive bonding material served such that the conductive binding material is located between the lead and electrode of one of the corresponding pairs.
Patent
Semiconductor device having offsetchips
TL;DR: In this paper, a semiconductor device comprises a square-shaped first semiconductor chip having a first linearisometry (LSI) and a squareshaped second semiconductor chips having a second LSI.