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[서평]「Computer Organization and Design, The Hardware/Software Interface」

Impedance-source networks cover the entire spectrum of electric power conversion applications (dc-dc, dc-ac, ac-dc, ac-ac) controlled and modulated by different modulation strategies to generate the desired dc or ac voltage and current at the output. A comprehensive review of various impedance-source-network-based power converters has been covered in a previous paper and main topologies were discussed from an application point of view. Now Part II provides a comprehensive review of the most popular control and modulation strategies for impedance-source network-based power converters/inverters. These methods are compared in terms of theoretical complexity and performance, when applied to the respective switching topologies. Further, this paper provides as a guide and quick reference for researchers and practicing engineers in deciding which control and modulation method to consider for an application in a given topology at a certain power level, switching frequency and demanded dynamic response.

Impedance-Source Networks for Electric Power Conversion Part II: Review of Control and Modulation Techniques

The tilt angle of a solar energy system is one of the important parameters for capturing maximum solar radiation falling on the solar panels. This angle is site specific as it depends on the daily, monthly and yearly path of the sun. The accurate determination of the optimum tilt angle for the location of interest is essential for maximum energy production by the system. A number of methods have been used for determining the tilt angle at different locations worldwide. Keeping in view the relevance of the optimum tilt angle in energy production and reducing the cost of solar energy systems, the present study has been undertaken. This paper provides the update status of research and applications of various methods for determining solar panel tilt angle using different optimization techniques. The study shows that for maximum energy gain, the optimum tilt angle for solar systems must be determined accurately for each location. The review will be useful for designers and researchers to select suitable methodology for determining optimal tilt angle for solar systems at any site.

Tilt angle optimization to maximize incident solar radiation: A review

This paper presents a novel electromyography (EMG)-driven hand exoskeleton for bilateral rehabilitation of grasping in stroke. The developed hand exoskeleton was designed with two distinctive features: (a) kinematics with intrinsic adaptability to patient’s hand size, and (b) free-palm and free-fingertip design, preserving the residual sensory perceptual capability of touch during assistance in grasping of real objects. In the envisaged bilateral training strategy, the patient’s non paretic hand acted as guidance for the paretic hand in grasping tasks. Grasping force exerted by the non paretic hand was estimated in real-time from EMG signals, and then replicated as robotic assistance for the paretic hand by means of the hand-exoskeleton. Estimation of the grasping force through EMG allowed to perform rehabilitation exercises with any, non sensorized, graspable objects. This paper presents the system design, development, and experimental evaluation. Experiments were performed within a group of six healthy subjects and two chronic stroke patients, executing robotic-assisted grasping tasks. Results related to performance in estimation and modulation of the robotic assistance, and to the outcomes of the pilot rehabilitation sessions with stroke patients, positively support validity of the proposed approach for application in stroke rehabilitation.

An EMG-Controlled Robotic Hand Exoskeleton for Bilateral Rehabilitation

In this paper, we propose the concept and design methodology for a resonant reactive shield for the reduction of magnetic field leakage from a wireless power transfer (WPT) systems. By using LC resonance, the reactive shield can generate a cancelling magnetic field to reduce the incident magnetic field from WPT coils and effectively reduce the total magnetic field without consuming additional power. The shielding effectiveness of the resonant reactive shield and its effect on WPT efficiency are analyzed with simulation and measurements. For practical application to wirelessly charged electric vehicles, an automatic tuning system for the resonant reactive shield is also proposed and implemented. The effectiveness of a resonant reactive shielding is verified by experiments in a wirelessly charged electric bus.

Design and Analysis of a Resonant Reactive Shield for a Wireless Power Electric Vehicle

The paper describes the design of high performance MIPS Cryptography processor based on triple data encryption standard. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of triple data encryption standard (T-DES) crypto system and dependency among themselves are explained in detail with the help of block diagram. In order to increase the processor functionality and performance, especially for security applications we include three new 32-bit instructions LKLW, LKUW and CRYPT. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The overall MIPS Crypto processor works at 209MHz. Keywords ALU, register file, pipeline, memory, T-DES, throughput 1. INTRODUCTION oday’s digital world, Cryptography is the art and science that deals with the principles and methods for keeping message secure. Encryption is emerging as a disintegrable part of all communication networks and information processing systems, involving transmission of data. Encryption is the transformation of plain data (known as plaintext) into inintengible data (known as cipher text) through an algorithm referred to as cipher. MIPS architecture employs a wide range of applications. The architecture remains the same for all MIPS based processors while the implementations may differ [1]. The proposed design has the feature of 32-bit asymmetric and symmetric cryptography system as a security application. There is a 16- bit RSA cryptography MIPS cryptosystem have been previously designed [2]. There are the small adjustments and minor improvement in the MIPS pipelined architecture design to protect data transmission over insecure medium using authenticating devices such as data encryption standard [DES], Triple-DES and advanced encryption standard [AES] [3]. These cryptographic devices use an identical key for the receiver side and sender side. Our design mainly includes the symmetric cryptosystem into MIPS pipeline stages. That is suitable to encrypt large amount data with high speed. The MIPS is simply known as Millions of instructions per second and is one of the best RISC (Reduced Instruction Set Computer) processor ever designed. High speed MIPS processor possessed Pipeline architecture for speed up processing, increase the frequency and performance of the processor. A MIPS based RISC processor was described in [4]. It consist of basic five stages of pipelining that are pipelined processor is shown in Fig.1 which containInstruction Fetch, Instruction Decode, Instruction Execution, Memory access, write back. These five pipeline stages generate 5 clock cycles processing delay and several Hazard during the operation [2]. These pipelining Hazard are eliminates by inserting NOP (No Operation Performed) instruction which generate some delays for the proper execution of instruction [4]. The pipelining Hazards are of three type’s data, structural and control hazard. These hazards are handled in the MIPS processor by the implementation of forwarding unit, Pre-fetching or Hazard detection unit, branch and jump prediction unit [2]. Forwarding unit is used for preventing data hazards which detects the dependencies and forward the required data from the running instruction to the dependent instructions [5]. Stall are occurred in the pipelined architecture when the consecutive instruction uses the same operand of the instruction and that require more clock cycles for execution and reduces performance. To overcome this situation, instruction pre-fetching unit is used which reduces the stalls and improve performance. The control hazard are occurs when a branch prediction is mistaken or in general, when the system has no mechanism for handling the control hazards [5]. The control hazard is handled by two mechanisms: Flush mechanism and Delayed jump mechanism. The branch and jump prediction unit uses these two mechanisms for preventing control hazards. The flush mechanism runs instruction after a branch and flushes the pipe after the misprediction [5]. Frequent flushing may increase the clock cycles and reduce performance. In the delayed jump mechanism, to handle the control hazard is to fill the pipe after the jump instruction with specific numbers of NOP’s [5]. The branch and jump prediction unit placement in the pipelining architecture may affect the critical or longest path. To detecting the longest path and improving the hardware that resulting minimum clock period and is the standard method of increasing the performance of the processor. To further speed up processor and minimize clock period, the design incorporates a high speed hybrid adder which employs both carry skip and carry select techniques with in the ALU unit to handle the additions. This paper is organized as follows. The system architecture hardware design and implementation are explained in Section II. Instruction set of MIPS including new instructions in detail with corresponding diagrams shown in sub-sections. Hardware implementation design methodology is explained in section III. The experimental results of pipeline stages are shown in section IV. Simulation results of encrypted MIPS pipeline processor and their Verification & synthesis report are describes in sub sections. The conclusions of paper are described in section V.

/pdf/design-of-high-performance-mips-cryptography-processor-based-1dze8z0txk.pdf

Design of High Performance MIPS Cryptography Processor Based on T-DES Algorithm

The paper describes the design of high performance MIPS Cryptography processor based on triple data encryption standard. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of triple data encryption standard (T-DES) crypto system and dependency among themselves are explained in detail with the help of block diagram. In order to increase the processor functionality and performance, especially for security applications we include three new 32-bit instructions LKLW, LKUW and CRYPT. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The overall MIPS Crypto processor works at 209MHz.

The paper describes the power and area efficient carry select adder (CSA). Firstly, CSA is one of the fastest adders used in many data-processing systems to perform fast arithmetic operations. Secondly, CSA is intermediate between small areas but longer delay Ripple Carry Adder (RCA) and a larger area with shorter delay carry look-ahead adder. Third, there is still scope to reduce area in CSA by introduction of some add-one scheme. In Modified Carry Select Adder (MCSA) design, single RCA and BEC are used instead of dual RCAs to reduce area and power consumption with small speed penalty. The reason for area reduction is that, the number of logic gates used to design a BEC is less than the number of logic gates used for a RCA design. Thus, importance of BEC logic comes from the large silicon area reduction when designing MCSA for large number of bits. MCSA architectures are designed for 8-bit, 16-bit, 32-bit and 64-bit respectively. The design has been synthesized at 90nm process technology targeting using Xilinx Spartan-3 device. Comparison results of modified CSA with conventional CSA show better results and improvements.

/pdf/design-of-high-speed-hybrid-carry-select-adder-4d6gnvzivt.pdf

Design of high speed hybrid carry select adder

This paper presents the design and implement a basic five stage pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000 nm2.

https://zenodo.org/record/33247/files/Vhdl_Implementation_of_A_Mips-32_Pipeline_Processor.pdf

Vhdl Implementation of A Mips-32 Pipeline Processor

The paper describes the Low power 32-bit encrypted MIPS processor based on AES algorithm and MIPS pipeline architecture. The pipeline stages of MIPS processor are arranged in such a way that pipeline can be clocked at high frequency and clock gating technique is used for reducing power consumption. Encryption blocks of Advanced Encryption Standard (AES) cryptosystem and dependency among pipeline stages are explained in detail with the help of block diagram. In order to reduce the power consumption, especially for portable devices and security application switching activity is used inside pipeline stages. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The encrypted MIPS pipeline processor can work at 210MHz and power consumption is 1.313W.

/pdf/low-power-encrypted-mips-processor-based-on-aes-algorithm-3m4mdcu1n9.pdf

Shivani Parmar

Papers

Design of High Performance MIPS Cryptography Processor Based on T-DES Algorithm

Design of High Performance MIPS Cryptography Processor Based on T-DES Algorithm

Design of high speed hybrid carry select adder

Vhdl Implementation of A Mips-32 Pipeline Processor

Low power encrypted mips processor based on aes algorithm