Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises growing a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions. The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Process for forming gate oxides possessing different thicknesses on a semiconductor substrate

A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Method for fabricating a semiconductor device

Disclosed is an example method of manufacturing a semiconductor device. The disclosed example method includes depositing a gate insulating layer on an active region of a self aligned silicide (salicide) region and a non-self aligned silicide (salicide) region of a semiconductor substrate, forming a gate electrode, a poly crystal silicon layer, on the gate insulating layer of the self aligned silicide (salicide) region, and forming a spacer on both sidewalls of the gate electrode. The example method may further include depositing a silicide shielding layer on the gate insulating layer to cover the gate electrode and the spacer, forming a photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region, removing the silicide shielding layer of the self aligned silicide (salicide) region to expose the gate electrode, and performing an ion-implantation to render the poly crystal silicon layer of the gate electrode amorphous, without removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region. The example method may further include removing the photoresist on the silicide shielding layer of the non-self aligned silicide (salicide) region and cleaning the semiconductor substrate and depositing a metal layer for forming a silicide layer and forming the silicide layer on the gate electrode of the self aligned silicide (salicide) region by annealing the semiconductor device.

Methods of manufacturing semiconductor devices

A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.

Shun-Liang Hsu

Papers

Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process