PURPOSE:To facilitate variable speed control by forming one end of the salient pole piece of winding in parallel with the circumferential end of a permanent magnet rotor extending in the axial direction of pole thereby making it possible to rise the rotation with a low voltage. CONSTITUTION:Angular width T of the salient pole piece 15 of a winding salient pole 8 in a stator armature core 7 is set equal to the pole width T of N pole 2N and S pole 2S of a permanent magnet 2, and the other end 15a of the salient pole piece 15 is formed in parallel with the axial direction of the poles 2N, 2S. A skew notched part 21 is provided at the other end 15b of the salient pole piece 15, over 1/4-3/4 pole width from one end of the salient pole piece 15, such that the area facing with the poles 2N, 2S of the permanent magnet rotor 2 of the salient pole piece 15 decreases gradually toward one end of the salient pole piece 15. Consequently, rising of rotation with low voltage is realized, variable speed control is facilitated and a large torque can be obtained.

Single phase cored brushless motor

A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

Semiconductor integrated circuit

PURPOSE:To call a user's attention to prevent data in a card from being broken due to its careless ejection by lighting up a light emitting element during the access period of the card. CONSTITUTION:A main control circuit 1 outputs an accessing signal to a signal line 9 only the reading and writing period of data in/from a memory circuit 12. During the outputting period of the accessing signal to the signal line 9, a driving circuit 5 is actuated and the light emitting element 4 is lighted up to inform that the memory circuit 12 is being accessed at present to the card user. A buffer circuit 3 has a function for electrically insulating both circuits 1, 2 during the period other than the outputting period of the accessing signal from the circuit 1. Consequently, the card can be prevented from being ejected by the user in error when the main control part is accessing the memory circuit in the card.

Terminal equipment for card

Signal transmitting circuit

PURPOSE: To provide a power management device which doesn't require the additional cost by providing a power management sequencer which sequences power management instructions obtained through an I/Q bus independently of a CPU instruction sequencer. CONSTITUTION: The power management device includes the power management sequencer which sequences power management instructions obtained through an I/Q bus 22 independently of the CPU instruction sequencer. These instructions are stored in a BIOS EPROM 48, and consequently, they can be customized by a manufacturer so that they include specific power management instructions required for peripheral devices included in a system. The BIOS EPROM doesn't cost the computer manufacturer additionally because it is included anywhere at need unless it purposes to include a proper initialization routine for the combination of a BIOS and specific attached peripheral devices.

Electric power management sequencer

PURPOSE:To avoid that the control of a controller using a common bus becomes impossible by allowing data to flow to the common bus from an input/output device having a fault. CONSTITUTION:Each bus, a data/control bus D/C and address bus IOA which are shown at the left side of a bus adaptor BA are connected to a controller via a common bus B. While the buses as shown at the right side of the BA are connected to the input/output device (one of I/O1-I/On or m units of I/On+1- I/On+m). In a static state, a gate flip-flop G-FF is reset at each bus adaptor. Then ''0'' is delivered from an output terminal Q. With this output, line drivers DV1 and DV2 are inhibited together with a line receiver RV. In other words, the output has a high impedance. Thus the bus B and the adaptor BA are cut off from the input/output device which controls the connection with the controller.

Bus controlling system

PURPOSE:To enable to avoid interference, by inhibiting the double write-in of the signal to the bus memory with the write-in control bit of the control memory and performing asymmetrical connection of the time sharing circuit network. CONSTITUTION:The bus memories SPMF1...SPMFn store the signal in time sharing multiplex, the control memories CM1...CMn write in the signal to the memories SPMF1...SPMFn in arbitrary address, and the counter CTR sequentially reads out the signal from the memories SPMF1...SPMFn. Further, the bus memories, control memories and counters are provided at the output side of the time sharing network. Further, the memories CM1...CMn are provided with the write- in control bit WI inhibit or enable the write-in of the signal to the memories SPMF1...SPMFn,and the control bit WI inhibits the double write-in of the signal to the memories SPMF1...SOMFn, for asymmetrical connection to the time sharing circuit network. Thus, interference can be avoided.

Shunichi Naito

Papers

Bus controlling system

Asymmetrical control system for time sharing network