S
Shunsaku Muraoka
Researcher at Panasonic
Publications - 102
Citations - 1611
Shunsaku Muraoka is an academic researcher from Panasonic. The author has contributed to research in topics: Electrode & Layer (electronics). The author has an hindex of 20, co-authored 102 publications receiving 1595 citations.
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Patent
Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor apparatus using the nonvolatile memory element
Yoshihiko Kanzawa,Koji Katayama,Satoru Fujii,Shunsaku Muraoka,Koichi Osano,Satoru Mitani,Ryoko Miyanaga,Takeshi Takagi,Kazuhiko Shimakawa +8 more
TL;DR: A nonvolatile memory element comprises a first electrode layer ( 103), a second electrode ( 107), and a resistance variable layer ( 106 ), which is disposed between the first electrode and the second electrode layer.
Patent
Writing method of variable resistance non-volatile memory element and variable resistance non-volatile memory device
TL;DR: In this article, a variable-resistance non-volatile memory element (VRSNVM) is written in a first determination step, in which it is determined whether or not a resistance state of the VRSVM does not switch to a first resistance state and remains in a second resistance state, when a pulse of a second voltage is applied to the variable resistance NVM.
Patent
Nonvolatile storage element, its manufacturing method, and nonvolatile semiconductor device using the nonvolatile storage element
Yoshihiko Kanzawa,Koji Katayama,Satoru Fujii,Shunsaku Muraoka,Koichi Osano,Satoru Mitani,Ryoko Miyanaga,Takeshi Takagi,Kazuhiko Shimakawa +8 more
TL;DR: In this paper, a nonvolatile storage element is provided with a first electrode layer, a second electrode layer and a resistance change layer, which reversibly changes on the basis of electrical signals given between both electrodes (103) and (107).
Patent
Memory device, memory circuit and semiconductor integrated circuit having variable resistance
TL;DR: In this article, a first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first node and the third node.
Patent
Resistance variable element and resistance variable memory apparatus
TL;DR: In this paper, a resistance variable element (10) consisting of a first electrode, a second electrode, and a resistor variable layer (3) is provided between the first electrode (2) and the second electrode (4) to be electrically connected to the first and second electrodes.